What goes through your mind when you think about the debug step in silicon chip verification? Do you start to cringe or feel a sense of dread as you anticipate countless, painstaking hours ahead? According to the latest 2021 Synopsys Global User Survey, system-level debug is still one of the top three verification challenges customers face. However, as time-consuming as the effort is, the earlier you can find and fix bugs in your design, the less costly it will be for your overall budget.
The variances involved in the debug process make the process painstaking and the results often unpredictable. First, you run stimulus against your RTL- or gate-level model to verify whether the model behaves as expected. If it doesn't, then the incident is tagged as an error. If you determine that the error is in the testbench, you might have to rewrite and rerun the testbench. If the error is in the design, sometimes it's superficial and you only need to run a few cycles of simulation. Often, you must run simulation for millions of cycles to find very deep corner case bugs that are embedded in the design. So, based on where the bug is and the number of lines of code involved, the time that's required to reach an answer will vary considerably.
Enhancing the debug process in terms of accuracy, speed, and exhaustive coverage is one of the most important verification challenges to solve. In this blog post, we'll discuss what makes debug so difficult, what to look for in a debug tool, and how advanced debug technologies can help ease the process.