What is Synthesis?

Synthesis begins with RTL code, which describes the behavior of a digital circuit in terms of registers, operations, and data flow. The synthesis process involves several key steps:

1. Parsing and Elaboration: The synthesis tool reads the RTL code, checks for errors, and builds an internal model of the design, resolving modules and hierarchies.
2. Technology Mapping: The tool translates the RTL logic into a network of standard logic gates and flip-flops that are part of the target technology library.
3. Optimization: The netlist is optimized for design goals such as minimal area, low power consumption, and high performance. Techniques like logic minimization, retiming, and resource sharing are commonly used.
4. Constraint Handling: Designers provide constraints such as clock periods, timing requirements, and area limits. The synthesis tool attempts to meet these constraints during optimization.
5. Output Generation: The final result is a gate-level netlist, which is used in downstream steps like physical design, placement, and routing.

Synthesis tools also provide feedback on how well the design meets specified goals. For example, they can estimate if the circuit will run at the desired clock speed or fit within a particular area budget. This feedback allows designers to refine their RTL code or constraints early in the design process.

Synthesis is closely linked to verification and testing. During synthesis, test structures can be inserted to make sure the manufactured chip can be efficiently tested for defects. Synthesis tools also work in conjunction with formal verification tools, which check that the gate-level netlist is functionally equivalent to the original RTL code, helping to catch errors before manufacturing.

RTL synthesis specifically refers to converting register-transfer level code into a gate-level netlist, while logic synthesis is a broader term that can include optimizations and transformations at various abstraction levels. In practice, these terms are often used interchangeably within the context of digital IC design.

Modern synthesis is evolving rapidly. Machine learning is being used to predict the impact of design changes and to improve optimization. Cloud-based synthesis enables faster turnaround for large-scale designs. Unified flows that combine synthesis with placement and routing are helping address the growing complexity and integration required for advanced chips.

Synthesis offers a range of important benefits to the semiconductor design process:

• Automation: Reduces manual effort by automating the translation from high-level design to manufacturable hardware.
• Optimization: Improves key design metrics such as power, performance, and area through advanced algorithms.
• Scalability: Handles increasingly complex designs, from small controllers to large system-on-chip (SoC) devices.
• Predictability: Provides early feedback on quality metrics, helping designers make informed decisions before physical implementation.
• Integration: Connects seamlessly with verification, testing, and physical design tools, streamlining the entire chip development process.
• Consistency: Ensures that the design intent is preserved from RTL through to silicon, improving reliability and yield.

Synopsys is a global leader in electronic design automation, providing synthesis solutions for both FPGA and ASIC design flows.

• For FPGA design, Synopsys offers Synplify®, a widely used synthesis solution that delivers high-quality results for programmable logic designs, with focus on auto insertion of safety and high reliability logic, ensuring highly efficient mapping and timing closure.
• For ASIC design, Synopsys provides Design Compiler®, the industry-standard RTL synthesis tool, and Fusion Compiler™, a unified RTL-to-GDSII flow that combines synthesis, placement, and routing. These solutions help engineers optimize power, performance, and area at advanced technology nodes.

All Synopsys synthesis tools support industry-standard hardware description languages such as Verilog, SystemVerilog, and VHDL. By adopting these solutions, engineering teams can accelerate convergence, gain early insight into design quality, and achieve competitive results in both FPGA and ASIC design.