EDA
System
IP
SolvNetPlus
Training & Education
Definition
Physical design in silicon chips is the process of transforming a chip's logic design (logic gates and their interconnections) into an actual layout that can be manufactured on a silicon wafer.
Silicon chips are designed with the help of EDA tools. There are many complex steps to design silicon chips, but at its simplest level the major steps are:
Architectural design: creating the high-level architecture of the chip
Logic design: translating the architecture into logic gates, or digital circuits
Physical design: laying out the logic gates physically on the chip and connecting them
Analysis and verification of the design: analyze the power, performance, power, and verify the design correctness
Tape out and fabricate the silicon chip: finalize the silicon chip design and send to foundry for manufacture
EDA tools are a suite of software (and some hardware) applications that help the designer to automate and simplify the complex steps above, saving chip designers an immeasurable amount of time and effort in designing such complex devices. Today’s silicon chips can contain billions of interconnected logic gates, and it would be impossible to create a silicon chip without the help of many EDA software and hardware design verification tools.
A key step in the silicon chip design journey is the physical design or layout. In this step, the logical design is complete and now is laid out physically on the silicon. This corresponds to the third step above - performed after the architectural and logic steps. This step effectively creates a physical layout from the logical description, or “netlist”.
After the physical design is complete, the final steps are to perform extensive analysis and verification of the design to ensure that it is manufacturable, and that it functions as originally designed.
| Step | Description |
| Architectural Design | Defines the chip’s high-level architecture |
| Logic Design | Translates architecture into logic gates and digital circuits |
| Physical Design | Creates the physical layout and interconnections |
| Analysis & Verification | Checks for power, performance, and correctness |
| Tape Out & Fabrication | Finalizes and manufactures the silicon chip |
How Does Physical Design Work?
Before the physical design can be performed by EDA software tools, a silicon die design database along with the chip’s logical design must be provided to the physical design tool. The design database is like a blank canvas to hold the physical (and logical) design and indicates to the tool the physical size and dimensions of the chip, and the logical design database contains the logic gates and their pin-to-pin connections.
The major steps of physical design include:
- Floorplanning: Defining the placement (or physical location) of major functional blocks (such as processors, memory, and interfaces) on the chip to optimize size, performance, and power consumption. These blocks are often decided before the logical design of those blocks are complete.
- Placement: Determining the locations of all standard cells (basic logic gates and components) within the chip’s layout area, aiming to minimize wire length and meet timing requirements.
- Routing: Creating the actual metal connections (wires) that connect the placed cells and blocks according to the logical design. This involves multiple layers of metal and must avoid congestion, signal interference, and shorting with other signals.
- Clock Tree Synthesis (CTS): Designing the clock distribution network to ensure that the timing signals reach all parts of the chip simultaneously and reliably. This is achieved using a clock signal common to all storage devices that synchronizes the design.
- Power Planning: Establishing the paths for power and ground connections to ensure that all components receive adequate power without excessive voltage drops.
- Design Rule Checking (DRC) and Layout Versus Schematic (LVS): Verifying that the layout adheres to foundry manufacturing constraints and matches the intended logical schematic.
- Physical Verification: Running simulations and checks to ensure the design will function correctly and reliably when fabricated. This is in contrast with functional verification, which ensures the design functions correctly at the higher, logical level. Any functional verification failures should be fixed before implementing the physical design.
The responsibility of the EDA tool is to transform the logical design into a physical design both correctly and optimally, requiring minimal manual work by physical design engineers. Given a logical design and empty physical design, there can be many possibilities for a particular physical design; it is not a puzzle with only one solution. The challenge is to arrive at a complete physical design that correctly implements the logical design, meets the designer’s power, performance, and area (PPA) targets, as well as physical design rules dictated by the silicon foundry that ultimately manufactures the silicon chip.
Benefits of Physical Design
EDA tools completely automate most physical design steps while considering designer-specified constraints. This allows engineers to guide the physical design result to meet their design specific requirements. Examples of constraints include:
Minimize routing congestion (density of routing wires)
Minimize placement density
Set minimum/maximum routing lengths for specified signals
Provide the fastest timing for critical paths
Minimize placement area
In addition to meeting designer constraints, EDA-driven physical design can also check design rules and ensure they are not violated, creating designs that meet foundry requirements. Examples of design rules include:
Minimum spacing between routes
Minimum wire widths
Cell density limits
Cell placement restrictions
Pin spacing
Modern EDA software tools take advantage of multi-core CPUs, multithreading, and other parallelism software and hardware technologies to speed physical design steps, which can be very time consuming, especially on larger multi-billion-gate designs. Physical design software handles designs of any size, from small chips to large system-on-chips (SoCs), which would be infeasible to design manually. They also support designs created using any foundry or silicon technology. Physical design software is constantly enhanced by EDA companies to adapt to new silicon technologies and packaging options.
By completely performing automated physical design, engineers can focus on higher-level design challenges and innovation, rather than tedious, low-level layout tasks.
What Solutions Does Synopsys Offer?
Synopsys offers comprehensive, automated physical design solutions that create optimal designs to meet demanding timing, power, and area requirements, while respecting individual designer constraints and directives. Synopsys products that offer automated physical design functionality include:
These products offer complete silicon design solutions of which physical design is a key part of. As unified environments, they provide feasibility exploration, prototyping, floorplanning, design, optimization, analysis, verification, and advanced packaging, all within the entire silicon chip design journey. Synopsys’ physical design solutions are integrated capabilities in the context of the entire flow, not a discrete, isolated design step. For example, the placement and routing steps are timing and area driven, which tightly connects optimization to the physical design. This provides chip designers with a complete end-to-end integrated solution instead of a set of disconnected software tools.
From early architectural exploration, design implementation, test, IP, software and hardware verification, Synopsys continues to drive the next wave of innovation in silicon chip design.
Figure 1 below shows a window into the physical design of a silicon chip in Fusion Compiler, showing logic gated placement (rectangles) and metal route shapes (color coded by layer).
Physical Design FAQ
Below are answers to common questions about physical design, its key concepts, and how it supports successful silicon chip manufacturing.
Logic gates are the basic building blocks for a silicon chip design. They are placed on a silicon chip and connected by logical connections and physical routing.
Also known as layout or place and route, physical design creates the physical placement and connectivity of logic gates in a silicon chip design.
Layout is the process of physically designing the silicon chip, also referred to as physical design and place and route.
Design rules are requirements set by silicon foundries to ensure the chip is manufacturable.
Constraints are requirements defined by chip designers that are used as inputs to the physical design tools. They include timing, wire width, wire spacing, placement restrictions, etc.
Continue Reading
3D Chips: Socionext Achieves Two Successful Tape-Outs in Just Seven Months
New Fujitsu Chip to Power Greener, Smarter Data Centers
10 Tips for First-Pass Silicon Success in AI Chip Development
How Multi-Die Designs Boost Automotive Chip Innovation
Adapt or Fall Behind: The Critical Need for Engineers to Master AI Technologies
