Adaptability – Key to Fast Prototyping

Today's high-performance SoCs demand the latest standards and features, sometimes even before they have been fully established by the standards bodies. In addition, competitive pressure pushes product developers to accelerate schedules while maintaining high-quality design, leaving little time for exploration or even interoperability considerations. This is where prototyping can alleviate some of the pressure. Physical prototyping (FPGA-based) enables the acceleration of SoC design in a number of ways, including speeding up RTL verification, system validation, and shifting left the software development schedule, just to mention a few. However, it is not without challenges such as mapping and clocking issues, turnaround time, and capacity limitations.

For developers to achieve the benefits of prototyping, they need to be able to prototype complete and flexible SoC systems. This requires physical systems, associated tools, and components to be adaptable and scalable to meet foreseeable and unforeseeable challenges.

The DesignWare IP Prototyping Kits offer one methodology for fast-paced adaptability, where a FPGA-ready reference design for a target IP is provided, including SoC integration logic, as well as the hardware and software elements needed to minimize associated bring-up and integration efforts. The IP Prototyping Kits also provide simulation and synthesis mechanisms, i.e. complete set of scripts and associated files, serving as a complete starting point for fast paced design development and interoperability acceleration.

To illustrate how IP Prototyping Kits help designers develop flexible systems quickly, let’s consider a use case where multiple IP Prototyping Kits from different IP families are interconnected to form a system. In this case study, the system includes a variety of interface IP: HDMI TX Host, MIPI CSI-2 Host and uMCTL2 with an emulated DDR4 multiPHY. Figure 1 shows one configuration to connect the kits into a system, where the HDMI TX and MIPI CSI-2 IP Prototyping Kits are connected in “satellite” configuration, while the uMCTL2 is provided as a “soft” IP Prototyping Kit targeted for a HAPS-80 prototyping system. The glue logic block refers to the additional logic required to interconnect all the target elements. In this case, a configurable DesignWare Interconnect Fabric for AMBA AXI core serves as an AXI bus managing agent, and a DesignWare Bridge from AMBA AXI to AMBA APB connects APB ports to the AXI bus structure.

When connecting multiple prototyping systems together, designers need to consider several hardware configuration challenges. In Figure 2, the “satellite” IP Prototyping Kit on a HAPS-DX system is connected to the larger HAPS-80 system. Connecting these systems requires designers to consider issues such as pin mapping, clocking and interrupts allocation. The IP Prototyping Kits may include an ARC® Software Development Platform (SDP) with an AXI tunnel module, which seamlessly extends a AXI bus connectivity from one HAPS systems to another. The AXI tunnel provides a pathway for two interrupt lines that can be daisy chained to reach the ARC SDP. For cases where more than two interrupt lines are required, designers can use a DesignWare Interrupt Controller core.

The satellite configuration can also pose challenges with the compatibility of the video signal format. For instance, the MIPI CSI-2 Prototyping Kit comes standard with a commercially available camera with RAW video format output. Such video format is incompatible with the HDMI TX IP given that it’s not within the CTA (Consumer Technology Association, formerly known as the Consumer Electronics Association, CEA) standards. A solution is to introduce a simple Video Bridge that performs the format conversion and enables compatibility.

Prior to connecting all of the IP together, designers can test two systems in isolation to verify interoperability. This can easily be achieved with IP Prototyping Kits, as they can be interconnected directly in what is referred to as a Kit-2-Kit configuration (Figure 3).

The Kit-2-Kit configuration enables focusing on specific functionality, in this case video format conversion. Since, video-related IP Prototyping Kits include a multimedia link port setup for the top module, it is a matter of simply connecting the HT3 cables to the proper connectors. The MIPI CSI-2 reference design included in the IP Prototyping Kit can be quickly augmented with a “video bridge” for format conversion, and because the kit includes a complete synthesis environment based on HAPS ProtoCompiler (with all necessary scripts and reference files), producing a new FPGA image can take less than an hour.

Anyone that has undertaken a design or prototyping project knows that things do not always go your way right away. However, the ability to locate and resolve issues in a short timeframe is of significant importance. For instance, when the Synopsys team first connected the kits as shown in Figure 3, no image was observed on the monitor connected to the HDMI TX Prototyping Kit, which caused some initial anxiety. However, knowing that the reference design was robust and had been tested with the provided hardware components, the team was able to immediately discard a wide number of possibilities and focus on a few likely culprits. The ARC SDP connected to the MIPI CSI-2 kit allowed for immediate verification that a video signal was properly generated. On the HDMI TX side, it was also immediately verifiable that the HDMI TX core was properly set up and, using the included pattern generator, that the output signal was reaching the corresponding PHY and monitor. IP Prototyping Kits include two example bitfiles, one with instrumented signals that permit visibility of the internal signals of the FPGA using the HAPS ProtoCompiler runtime, which was used to verify that a video signal was being received. However, observing the instrumented signals was enough to note that although the number of pixels being transferred seem appropriate, they appeared to be compressed. A quick check of the databook revealed the need to switch the source clocks, since the default source clock is set up for an internal reference. And finally, the image showed on the monitor—success!

Once the “video bridge” functionality is verified, the target setup can be completed. For a multiple IP Prototyping Kit scenario, designers will need to make adjustments to the device tree for the provided reference software. To minimize changes to the designs provided in the IP Prototyping Kits, designers can filter the address target at the AXI tunnel level within the main HAPS board. By doing this, the targeted regions of the software are kept transparent to the hardware modules. An additional consideration for the software aspects are proper assignment of the interrupts allocation.