Today's high-performance SoCs demand the latest standards and features, sometimes even before they have been fully established by the standards bodies. In addition, competitive pressure pushes product developers to accelerate schedules while maintaining high-quality design, leaving little time for exploration or even interoperability considerations. This is where prototyping can alleviate some of the pressure. Physical prototyping (FPGA-based) enables the acceleration of SoC design in a number of ways, including speeding up RTL verification, system validation, and shifting left the software development schedule, just to mention a few. However, it is not without challenges such as mapping and clocking issues, turnaround time, and capacity limitations.
For developers to achieve the benefits of prototyping, they need to be able to prototype complete and flexible SoC systems. This requires physical systems, associated tools, and components to be adaptable and scalable to meet foreseeable and unforeseeable challenges.
The DesignWare IP Prototyping Kits offer one methodology for fast-paced adaptability, where a FPGA-ready reference design for a target IP is provided, including SoC integration logic, as well as the hardware and software elements needed to minimize associated bring-up and integration efforts. The IP Prototyping Kits also provide simulation and synthesis mechanisms, i.e. complete set of scripts and associated files, serving as a complete starting point for fast paced design development and interoperability acceleration.
To illustrate how IP Prototyping Kits help designers develop flexible systems quickly, let’s consider a use case where multiple IP Prototyping Kits from different IP families are interconnected to form a system. In this case study, the system includes a variety of interface IP: HDMI TX Host, MIPI CSI-2 Host and uMCTL2 with an emulated DDR4 multiPHY. Figure 1 shows one configuration to connect the kits into a system, where the HDMI TX and MIPI CSI-2 IP Prototyping Kits are connected in “satellite” configuration, while the uMCTL2 is provided as a “soft” IP Prototyping Kit targeted for a HAPS-80 prototyping system. The glue logic block refers to the additional logic required to interconnect all the target elements. In this case, a configurable DesignWare Interconnect Fabric for AMBA AXI core serves as an AXI bus managing agent, and a DesignWare Bridge from AMBA AXI to AMBA APB connects APB ports to the AXI bus structure.