One of the biggest decisions you can make in fabless semiconductor design is whether to go with a Customer Owned Tooling (COT) model or outsource to an ASIC vendor. The COT model can have a DIY cost advantage, but only if the chip volumes are high enough, and this also assumes that you have your own back-end teams and tools, as well as the operations and infrastructure, foundry relationships, and testing capability, to bring your designs to silicon. This can be a problem if you aren’t operating at the scale of the bigger industry players. If not, you’d likely choose an ASIC vendor to handle your chip development and manufacturing for you. While you give up some customizing control, you assume much lower risk. All you need to do is provide the front end of your design to your chosen ASIC vendor and wait for your chips to come back.
How can a similar, application-specific model map to the IP portion of your design? While IP may give you standard functions, the process to integrate these functions into your high-end designs isn’t standard at all. To use IP, you must navigate inconsistencies in your design’s component parts, such as the number of lanes, the clock speeds, the number and types of I/Os, and much more. The differences in variables such as these vary by application.
Having an application-specific, ease-of-use integration model for IP blocks can help you overcome these hurdles. Similar to the ASIC model, IP that encompasses an entire solution for the application can be effective in delivering lower cost and risk, using fewer resources, and improving time to market.
Most applications require different customizations. A good example is a PCI Express® (PCIe®) interface where the power, performance, area, and latency (PPA&L) tradeoff can vary significantly depending on whether the application is high-performance computing (HPC), storage, automotive, mobile, or some other application. If PCIe IP is going inside a server, for instance, it needs high performance to be able to bridge the distance between chips—as much as 12 to 14 inches. In this application, good performance takes precedence over power. This is not the case for a battery-powered mobile device which requires low-power states and can trade-off performance for that end.
Synopsys has built IP that goes beyond the block itself to an entire solution for different application scenarios. These solutions address the needs of the application, whether it differentiates on various features, technical PPA&L, or customer-specific customizations, including metal stacks, pitches, or another unique requirement.