Delivering LPDDR6 Read/Write Eyes at 10.67 Gb/s — Powering Memory for Mobile, AI & Embedded Systems

In the era of pervasive intelligence, memory bandwidth and energy efficiency are critical differentiators. The newly published JEDEC JESD209-6 standard for LPDDR6 represents a major leap forward. At Synopsys, our LPDDR6/5X/5 PHY IP has achieved clean read and write data eyes at the maximum 10.67 Gb/s per-pin data rate supported by the first LPDDR6 SDRAM samples, validating signal integrity, training robustness, and silicon readiness for next-generation platforms.

This milestone follows our recent silicon bring-up of the Synopsys LPDDR6 IP on TSMC’s N2P process, marking a significant step in enabling early ecosystem adoption. As Dino Toffolon, SVP of Engineering for Interface IP at Synopsys, noted: 

“We’re pleased to share our recent silicon bring-up on TSMC’s N2P process with our LPDDR6 IP. This achievement provides access for our customers to trusted IP for the most demanding mobile, edge AI, and HPC applications.” 

Together, these results affirm that LPDDR6 is no longer confined to mobile—it is now a foundational memory technology spanning AI, HPC, automotive, edge compute, consumer, and beyond.

Our validation results highlight:

• Stable read/write eyes at 10.67 Gb/s per pin with ample horizontal and vertical margins after full PHY training.
• Robust equalization using Rx DFE and on-die termination (ODT) tuning to improve timing and jitter margin.
• Silicon correlation between simulation, channel modeling, and measurement on Synopsys test platforms and 2nm silicon.

JEDEC’s LPDDR6 standard defines starting data rates of 10.67 Gb/s, scaling toward 14.4 Gb/s as the ecosystem matures. Reaching this initial speed with clear, repeatable eyes validates both the signal integrity of the design and readiness for higher speed operation in future revisions. This achievement ensures early adopters can move forward with confidence in timing budgets, channel designs, and system power envelopes.

While Synopsys has shown interoperability with the first SDRAM samples at 10.67Gbps, the maximum speed of those first DRAMs, we have also demonstrated the memory interface IP can support higher data rates of up to 14.4Gbps using ATE test capability of the IP as shown in Figure 2.  These test results add confidence that the IP can support higher data rates as the DRAM vendors release faster products in the future.

LPDDR6 introduces several innovations that strengthen performance-per-watt and scalability across domains:

• Dual-channel organization (2×24-bit) supporting wider effective widths and improved efficiency.
• Roadmap to 14.4 Gb/s operation, doubling effective bandwidth compared with LPDDR5X.
• Dynamic Voltage Frequency Scaling for Low Power (DVFSL) to dynamically adjust bandwidth and power.
• Improved reliability with on-die ECC, CA parity, and activation-tracking for row-hammer mitigation.
• Cross-market applicability—architected for mobile, HPC, AI, automotive ADAS, consumer, and embedded edge devices.

The distinction between mobile and compute memory is blurring. LPDDR memory, which was traditionally associated with mobile devices, is now expanding into areas like data centers with the introduction of the LPDDR6 standard. This has been facilitated via the inclusion of RAS features into LPDDR6 that were previously only supported in the domain of DDR5 along with significant capacity increases for LPDDR6 SDRAMs and modules.  Early silicon results show that LPDDR6 is well-suited to meet the performance, capacity and power efficiency demands of next-generation intelligent systems.

“LPDDR6 revolutionizes how memory and storage collaborate by leveraging Micron’s leadership in low-power DRAM alongside our advanced NAND and SSD technologies. Micron’s continued engagement with Synopsys on LP co-simulation, sample enablement and collateral sharing strengthens the on-going partnership as Micron’s LP innovation delivers higher bandwidth and ultra-low power consumption, enabling next-generation solutions to achieve superior performance and energy efficiency. Combined with ecosystem advancements from partners like Synopsys, these breakthroughs ensure seamless adoption and scalability across the industry”, said Gayathri Rao Subbu Director, Ecosystem Development for Cloud Memory Business Unit at Micron.

"Aligning with the technical preparation of Synopsys' LPDDR6 IP, Samsung expects to deliver LPDDR6 to the market quickly, and expects the consumer personal device, data center, automobile industry to experience the performance and low power of SAMSUNG LPDDR6", said Jangseok Choi, VP Leader of Product Planning Team at Samsung.

“Rising performance demands in premium smartphones, automotive systems, and client AI devices make LPDDR6 an important step forward for low-power DRAM. Synopsys plays a meaningful role in supporting the transition to this new standard across the diverse applications that depend on SK Hynix memory”, said, Sangkwon Lee, DRAM Product Planning VP at SK Hynix

To help drive the transition to LPDDR6, Synopsys delivers a complete IP solution that integrates the controller, PHY, and security and verification IP. Early silicon validation demonstrates robust operation at 10.667 Gb/s on advanced GAA technology, reinforcing confidence across the industry. 

Demonstrating clean read and write eyes at 10.667 Gb/s per pin establishes the foundation for LPDDR6 system validation and highlights our leadership in next-generation memory interfaces. As HPC, AI, automotive, consumer, and edge markets demand higher bandwidth within tight power envelopes, LPDDR6 will define the balance between performance and power efficiency.