A Bumblebee Moment for AI Silicon

AI silicon is entering a new phase. The industry is moving from broadly programmable acceleration toward architectures that are designed around specific workloads. That shift creates a new kind of validation challenge. It is no longer enough to verify that individual blocks function correctly or that simplified test cases pass. For workload-specific AI chips, the real question becomes much more direct: can the system execute the workload it was built for, correctly and efficiently, and can you confirm it before you commit to silicon?

That question was at the center of one of the most interesting presentations in this year’s Hardware-Assisted Verification track at Synopsys Converge Silicon Valley. Etched presented its work on Sohu, a transformer engine built specifically for AI inference. It was amazing to see how David Svensson from Etched build a development platform that enabled 40 software developers, using a 2 min iteration cycle for his complex AI project.

Since my parents had a car dealership, I have always been a car guy. The idea of Bumblebee — a familiar machine that transforms into something far more capable than it first appears — has always stayed with me. Etched’s story has a similar quality, but the transformation here is not cosmetic. The company is not adapting a general-purpose GPU architecture to transformer inference. It is building silicon around the workload itself. That distinction matters because the validation strategy has to transform as well.

For a purpose-built transformer ASIC, generic validation is not enough. The workload becomes the proof point.

The larger and more specialized AI chips become, the harder it is to rely on traditional validation approaches alone. Transformer inference stresses compute, memory, firmware, drivers, scheduling, and hardware/software interfaces at the same time. These interactions are precisely what make the chip valuable, but they are also what make verification and validation difficult.

For Sohu, Etched targets billion-parameter large language models with massive memory footprints and complex memory hierarchies. Full-system simulation cannot keep pace with production-scale workloads because those workloads can take weeks or months to run. Smaller tests are useful for debug and early development, but they do not exercise the design the way the final application will. And if the validation environment models memory, interfaces, or system timing too optimistically, the team may gain confidence in behavior that does not reflect how the silicon will operate in a real system.

This creates the central dilemma for AI accelerator validation. If the workload is simplified too much, the test becomes manageable but less meaningful. If the full workload is preserved, software simulation becomes too slow to support daily development. And if system context is abstracted away, the test may miss exactly the issues that determine whether the chip performs as expected.

Etched chose a more direct path: run the real workload in emulation. Instead of shrinking the problem, the team built an infrastructure that could handle it.

The strongest idea in the presentation is also the simplest: validate the chip by running the workload it is designed to execute.

For Sohu, that means executing a complete Llama 8-billion-parameter inference workload on ZeBu emulation. The workload streams billions of parameters through HBM via DMA, exercises the memory subsystem, validates data integrity, and processes one million tokens across 32 transformer layers with no loss of accuracy.

That scale matters. “as David Svensson from Etched described during his presentation, transformer inference does not activate only one part of the design. It brings DMA engines, memory hierarchy, systolic arrays, command dispatch, scheduling, synchronization, firmware, drivers, and software orchestration into the same environment. The DMA engines expose throughput, latency, and burst behavior. The memory hierarchy reveals caching behavior, bandwidth limits, and real access patterns. The systolic array drives compute across all 32 layers. The software stack coordinates the complete process under realistic system load.

This is where many system-level bugs live. They do not appear when teams test a single block in isolation. They appear when software, interfaces, compute, and memory interact at production scale. Etched’s approach recognizes that the actual workload — not a simplified proxy — must become the validation target.

Running a production-scale transformer workload before silicon requires more than raw emulation capacity. It requires an operating model that makes emulation available, repeatable, and useful for everyday engineering work.

Etched deployed 16 units of ZeBu Server 5 for complete Sohu chip emulation. Around that emulation environment, the team built a compute infrastructure with 48 servers: 16 connected to the ZeBu runtime environment and 32 supporting model build. The team also created a compilation and emulation job execution flow to make the environment usable at scale.

One of the most important elements is Etched’s internal always-on manager. It orchestrates emulation runs, reduces model reload overhead, and helps software teams use the platform productively. That changes the development flow. Software iteration time drops from six minutes to two minutes, enabling 40 software developers to use the ZeBu hardware and supporting more than 30 validation runs per hour.

For a startup building ambitious silicon, that productivity matters as much as emulation horsepower. Emulation delivers its full value only when teams can access it frequently, automate it reliably, and integrate it into daily engineering workflows. Etched turns the emulation platform into a shared pre-silicon development environment rather than a specialized resource used only by a small verification team.

That is an important shift. The value is not simply that the chip can run in emulation. The value is that hardware, software, firmware, and validation teams can work against the same pre-silicon system before silicon is available.

Etched also avoids the trap of running every test at full-chip, full-workload scale. That would be impressive, but not practical for daily development. Instead, the team uses a three-level validation hierarchy.

Scoped component tests support smaller models and fast daily development. Layered integration tests validate cross-component behavior at medium scale. Full LLM runs execute at lower frequency but provide the highest level of confidence.

This hierarchy balances speed and proof. Smaller tests help engineers iterate quickly and debug locally. Integration tests expose issues that appear across subsystems. Full LLM runs demonstrate whether the complete system can handle the workload that matters most.

The workflow follows three steps: model development, inference execution, and verification. During verification, the team extracts results, compares them bit-exact against a golden C reference model, and automates pass/fail reporting. Automation is essential because manual execution cannot keep expensive emulation resources fully utilized and introduces too much room for error.

This hierarchy is a practical example of what AI-era validation increasingly requires. Teams need fast paths for daily engineering progress and high-confidence paths for system-level proof. One does not replace the other. Both are necessary.

For a transformer chip, correctness and performance must be validated together.

Etched validates functional correctness through bit-exact matching against the golden reference. The flow uses zero-tolerance validation: no approximations, no sampling, and every computation verified. That level of accuracy matters because transformer inference is numerically sensitive. Small deviations can accumulate across layers and tokens. A validation strategy that samples too lightly may miss issues that only appear at full scale.

Performance receives the same attention. The team measures systolic array utilization, validates compute efficiency at scale, analyzes memory bandwidth, identifies congestion points and bottlenecks under production conditions, and measures real end-to-end throughput in production mode.

These are not synthetic benchmarks. They map directly to the behavior expected from silicon.

This distinction is important. A design can produce correct answers and still fail to meet performance expectations because of memory congestion, arbitration effects, synchronization delays, scheduling behavior, or inaccurate interface assumptions. For workload-specific silicon, performance is not a late-stage measurement exercise. It is part of validation from the beginning.

One of the most valuable lessons from the presentation concerns interface modeling. Performance data is only useful if the external interfaces behave realistically.

Etched identifies three traps. Zero-delay models can make performance look unrealistically good because they hide congestion. Fixed-delay models can miss arbitration and congestion effects under load. Overly optimistic models can lead software and firmware teams to optimize for the wrong target.

Each trap creates the same risk: the team believes it has validated system performance, while the validation environment quietly removes the conditions that expose real bottlenecks. Only transactors which perform an accurate representation of the interface protocol allow for real benchmarking of the systems behavior.

For AI systems, the boundary between the accelerator and the rest of the system becomes a critical validation target. Memory behavior, DMA traffic, firmware control, software scheduling, and interface timing all shape real performance. The principle is clear: real workloads require realistic system context.

Etched validates the software layer, hardware/software interface, compute layer, and memory layer together because queuing effects, scheduling races, synchronization bugs, and other emergent behaviors appear only when the full system is active.

The results are concrete. Etched proves functional correctness, validates performance, and enables 40 software developers to use the model before silicon arrives. Its always-on manager cuts iteration time from six minutes to two minutes, enabling more experimentation and supporting more than 30 validation runs per hour.

The workload itself is substantial: eight billion parameters, one million tokens processed, 32 transformer layers, and no loss of accuracy. The validation stresses DMA engines, memory hierarchy, compute pipelines, and hardware/software orchestration under real workload conditions rather than simplified test cases.

For me, the most important takeaway is that Etched does not treat emulation as a late-stage hardware check. It uses emulation as a pre-silicon development and validation platform. Software teams become productive before silicon. Drivers and firmware move earlier. Production-scale data supports tape-out decisions. And the team validates both correctness and performance under conditions that reflect the workload the chip is built to execute.

That is the real transformation.

Etched’s story reflects a broader shift in hardware-assisted verification. As AI chips become more workload-specific and software-driven, HAV has to do more than accelerate RTL execution. It has to provide an environment where teams can run production-scale workloads, validate hardware and software together, model interfaces accurately, measure realistic performance, and make software teams productive before silicon.

This is why the Etched example matters beyond one chip and one workload. It shows how validation is changing as AI silicon becomes more specialized. The proof point is no longer just whether the design is functionally correct in isolation. The proof point is whether the system can execute the real workload, at scale, under realistic conditions, early enough to influence design decisions.

That is the Bumblebee moment for AI silicon. The emulation environment transforms from a hardware model into something more powerful: a pre-silicon development platform where the real workload runs, software teams engage, performance becomes measurable, and the path to silicon becomes clearer.

For AI-era chip design, that transformation may become one of the most important verification shifts of all.

Find the Etched-Synopsys success story here.

• Validating Large Language Model Inference on ZeBu: A Llama 8B Case Study — David Sevensson, Etched AI, Synopsys Converge Silicon Valley 2026.
• Xavigivax, “Bumblebee from Transformers (2007) using a 1977 Chevrolet Camaro,” Picture source: Wikimedia Commons — licensed under CC BY-SA 3.0.
• Software-Defined Hardware-Assisted Verification: A New Benchmark for AI-Era Chip Design — Frank Schirrmeister, Tom De Schutter.