AI workloads are bringing to light a longstanding constraint in data centers: as bandwidth rises, copper paths consume more power and generate more heat.
Co-packaged optics (CPO) can help address this constraint. By bringing optical engines closer to compute and memory silicon, CPO shrinks the distance signals travel through copper.
In this Q&A, Sanjay Gangadhara, senior architect at Synopsys, discusses why the architectural approach is gaining urgency — and what it will take to make it work at scale.
Sanjay Gangadhara, Senior Architect, Synopsys
For a long time, fiber optics have been used to transmit data over long distances because optics is much more efficient than copper at those distances.
Traditionally, fiber brings data up to the front panel of a rack and then copper takes over. Optical signals are converted to electrical signals, which then travel to compute, memory, or other resources within the system. As the signal leaves, it is converted back to optics to get to the next rack.
But as you push more data at higher bandwidths through these systems, the power loss becomes significant and unsustainable.
With CPO, you remove some copper from the system and replace it with optics. Rather than taking light only to the front panel, you bring light all the way to the chip. The optical engine that performs the conversion between light and electrical signals sits on the same substrate in the same advanced package as the electronics.
The pace at which AI has moved over the last few years has changed the conversation. CPO has gone from being something that would be “interesting to explore in the future” to something that people feel they have to have now.
The primary benefit of CPO is lower power consumption. When you run current through copper, you lose power due to resistive heating. Light transmitted through fiber does not experience the same resistive loss and is generally much more efficient.
At the scale of AI data centers, the energy cost of moving data can’t be ignored.
It’s a harder design challenge. As you stack electronics and photonics together, you have to account for multiphysics effects like thermal and electrical crosstalk. Photonic components are very sensitive to temperature, so you have to understand the thermal profile across the full 3D device.
Reliability is another important issue. With a pluggable architecture, it is relatively easy to identify a failure and switch out the module. It’s like changing out a spark plug in your car. If a photonic integrated circuit (PIC) fails in a co-packaged architecture, you may need to replace the whole chip. That is much more expensive and leads to longer downtime.
People need to feel confident in the reliability and robustness of these designs before they can move in this direction. With advances in simulation, we are in a much better position than we were five years ago to address the multiphysics design and reliability challenges associated with CPO.
It’s a mix. There are companies selling commercial solutions, while others are still in R&D and developing what they believe will be competitive solutions.
But CPO is no longer just a concept. The question is whether the lower power consumption and higher performance over time justify the higher complexity and potential downtime if a failure occurs. For some applications, the market is signaling the benefits now justify the tradeoffs.
Cost is a major consideration. Designing a new device with a new architecture isn’t free. Reliability, manufacturability, and manufacturing capacity are also considerations.
Familiarity with existing solutions is another factor. Some companies believe they can continue to get more out of copper-based approaches. They understand copper well, they know its limits, and they may feel they can move faster by incrementally improving an existing solution rather than trying a completely new one.
But CPO is not a wholesale replacement for electrical interconnects. As long as you have electrical compute and memory on the chip, you will have some level of electrical interconnects in the system. Companies are evaluating where the right balance is among cost, robustness, performance, reliability, and what they can produce today.
Standards will eventually be required to reach the scale and volume that make CPO competitive with more traditional architectures. Today, much of the work remains highly customized, especially on the photonics side.
There is a big effort in the industry to develop standards, but it is still fragmented. Eventually, the ecosystem will need common frameworks that allow companies to differentiate on cost, robustness, and reliability.
It will take a few years to get there. Photonics is still relatively immature compared to electronics, and companies are working hard to squeeze the last bit of performance out of their custom designs. A more standardized ecosystem will be needed to reach greater scale and volume.
You have to think about the system-level design. You cannot optimize each individual element separately and then bring them together like LEGO bricks.
As you stack these chips in a 3D design, you have to maximize the efficiency of the power-delivery network and minimize electrical and thermal interference. You also need robust physics analysis to evaluate the full thermal and electrical profiles across the 3D device.
Addressing those challenges requires a unified view of electronics, photonics, packaging, and system behavior. Synopsys brings together photonic design and multi-die implementation tools with optics and photonics simulation and integrated multiphysics analysis capabilities to support system-level CPO design.