SNUG 2019 Verification Lunch Panel

SNUG 2019 Verification Lunch Panel

SoC Leaders Verify with Synopsys

On March 20, 2019 Synopsys hosted a luncheon event at the annual Synopsys Users Group (SNUG) in Santa Clara, CA. At this event, Johannes Stahl delivered an update highlighting new Verification Continuum™ solutions for ZeBu® Server 4, HAPS®-80 Desktop Prototyping and VC Formal™ Regression Mode Accelerator App.

Krishna Tadi (Samsung) spoke about “Emulation for Verification”, Sreekanth Ramani (Intel) spoke about “System Power Validation on FPGA Platforms” and Michael Posner (Synopsys) closed with a presentation on “DesignWare IP Validation with HAPS Prototyping Systems”. 

Speakers

Johannes Stahl

Senior Director, Product Marketing for Verification Group, Synopsys
SoC Leaders Verify with Synopsys

Krishna Tadi

Staff Engineer, Samsung
Emulation for SoC Verification

Sreekanth Ramani

Manager & Technical Lead for Pre-silicon Strategies & Capabilities, Intel
System Power Validation on FPGA Platforms

Michael Posner

Director of Product Marketing
DesignWare IP Validation with HAPS Prototyping Systems