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Key Takeaways
- Scale of the buildout: McKinsey projects that data centers will require $6.7 trillion in capital investment worldwide by 2030 to build enough capacity to keep pace with demand for compute — $5.2 trillion of it for AI-capable facilities — with about 70% of new capacity demand coming from AI workloads.
- Power is the binding constraint: US data centers consumed 76 TWh in 2018, 1.9% of US electricity. By 2028, the projection is 325 to 580 TWh, or 6.7 to 12% of national energy (Lawrence Berkeley National Laboratory).
- Cooling is the largest overhead: As much as 40% of the power used in an AI data center is consumed by the systems that keep the chips cool, rather than by the compute hardware (Ansys).
- The constraints interact across scales: Performance, power, and thermal limits couple from the transistor through the rack to the building. Optimizing one scale in isolation can shift the problem rather than solving it, which is why AI facility design is an analysis problem before it is a construction problem.
Definition
An AI and HPC data center, also known as an AI factory, is a facility purpose-built for artificial intelligence and high-performance computing workloads, distinguished by accelerator-dense racks, custom silicon, liquid cooling, and rack power densities several times higher than traditional facilities.
What Are AI and HPC Data Centers?
A data center houses the computing infrastructure, such as servers, storage, networking, and the power and cooling systems that support them, that organizations use to process and store data. AI and HPC data centers, also known as AI factories, are variants built for the most compute-intensive workloads in existence: large-scale AI model training and inference, scientific simulation, financial modeling, weather forecasting, genomics, and the high-bandwidth data movement that connects them.
High-performance computing data centers predate the current AI buildout by decades. They were built for scientific and engineering simulation, which worked on fluid dynamics, molecular modeling, and seismic analysis, where massively parallel computation was the only practical route to problems too large for a single machine. What has changed is that AI workloads now demand the same architectural characteristics HPC pioneered: dense parallel compute, high-speed interconnect, and cooling built for sustained high-power operation. The result is a convergence. Most modern AI facilities are, architecturally, HPC facilities, and the two terms are increasingly used together.
What separates either from a traditional facility is the hardware inside. Where a conventional data center runs general-purpose processors at moderate power density, an AI or HPC facility packs racks with AI accelerators and custom silicon built for parallel computation. That change in silicon drives everything downstream, including the power delivery architecture, the cooling system, the physical footprint, and the engineering needed to keep the facility running.
Figure 1. Four dimensions that separate an AI or HPC facility from a traditional one. Silicon, rack power density, cooling method, and workload profile. Each difference follows from the one above it: the silicon sets the density, the density sets the cooling method, and the workload profile determines how sustained the load is.
AI Factories and AI Data Centers: How the Terms Relate
"AI factory" has become the common term for this class of facility, and it describes something slightly narrower than "AI data center". The distinction that has settled in practice is one of scope. An AI data center is the facility: the building, the power infrastructure, the cooling plant, and the accelerator-dense compute it houses. An AI factory is that facility understood as a production system, engineered end to end for the full model lifecycle of training, fine-tuning, and inference.
The framing originated with Nvidia, which uses it deliberately to move the mental model away from a building that stores servers and toward a plant that manufactures intelligence, taking data and electricity as raw materials and producing tokens as output. It has since moved beyond any single vendor. Omdia now tracks AI Factory as a market category in its own right, describing it as having crossed an irreversible threshold into an industrialization era, with 2026 and 2027 as the critical window for buildout.
Both terms describe the same physical engineering problem, which is why this guide treats AI and HPC data centers as the umbrella and uses AI factory where the production framing is what matters. Every AI factory is an AI data center; not every AI data center runs the full AI lifecycle that makes it one.
Three Operational Profiles
AI and HPC facilities fall broadly into three profiles, and many modern sites combine all three:
- Training clusters are optimized for the sustained, weeks-long workloads that build foundation models. Load is high and relatively constant once a run begins.
- Inference farms are optimized for low-latency, high-throughput serving of trained models. Load is variable and follows demand.
- HPC simulation facilities are built for sustained scientific and engineering computation, often with different interconnect and storage priorities than AI training.
Each profile carries distinct requirements for compute density, network bandwidth, and thermal management. All three share the same underlying constraint: more work per watt and per square foot than any previous generation of facilities.
Why AI and HPC Data Centers Are Different
The Demand Surge
The scale of investment has no clear precedent in the technology industry. McKinsey projects that data centers will require $6.7 trillion in capital investment worldwide by 2030 to keep pace with demand for compute power, of which $5.2 trillion is for facilities equipped to handle AI processing loads and $1.5 trillion for those running traditional applications. Global demand for data center capacity could almost triple by 2030, to 219 GW, with about 70% of that new demand coming from AI workloads. For scale, that is roughly a sixth of total US electricity generating capacity, which stands at close to 1,400 GW — or, put another way, about a hundred Hoover Dams running at full output. Power demand for AI workloads specifically is projected to rise from 44 GW in 2025 to 156 GW by the end of the decade.
The near-term capital numbers are equally steep. BloombergNEF puts the 2026 capital expenditure of the 14 largest publicly owned data center operators close to $750 billion, against a little less than $450 billion the prior year. At the end of September 2025, more than 23 GW of data center IT capacity was under construction globally, roughly three-quarters of it in the United States.
The Power Density Shift
A traditional enterprise rack draws 5 to 15 kW. An accelerator-dense AI training rack runs from 30 kW to over 100 kW. That increase cascades through every downstream system: power distribution, uninterruptible supply sizing, busbar and cable routing, and above all, cooling.
Figure 2. US data center power consumption, measured and projected. Consumption reached 76 TWh in 2018, 1.9% of US electricity. The 2028 projection is a range — 325 to 580 TWh, or 6.7 to 12% of national energy — and the width of that range is itself the finding. Source: Lawrence Berkeley National Laboratory.
At the national scale, the numbers are stark. According to the Lawrence Berkeley National Laboratory, US data centers consumed 76 TWh in 2018, representing 1.9% of total US electricity consumption. By 2028, the projection is between 325 and 580 TWh, or 6.7 to 12% of total US energy. The width of that range matters: it reflects genuine uncertainty about buildout pace and efficiency gains, and quoting only its upper bound overstates what the source claims.
Globally, Goldman Sachs Research projects that data center power demand will grow 160% by 2030.
Custom High-Performance Silicon
Traditional general-purpose processors are not built for the massively parallel matrix operations that dominate AI and HPC workloads. Accelerators, custom AI silicon, and purpose-built HPC systems-on-chip deliver order-of-magnitude improvements in throughput per watt for training, inference, and simulation.
Architecting, designing, simulating, and validating these chips are a vast set of difficult engineering challenges themselves. As the Synopsys HPC & Data Center Solution describes it, processing high volumes of data at minimum power consumption for these workloads now requires advanced silicon process nodes, high-speed interface IP including SerDes, and 2.5D or 3D advanced packaging, alongside hardware and software co-optimization and early architectural exploration to meet demanding schedules. These advanced designs must be simulated not only for correct functionality but also verified for timing, multiphysics effects, and a complex and ever-growing set of design rules.
The Power and Cooling Challenge
Power and the Grid
Deloitte projects that critical power supporting data centers, processors, storage, cooling, and networking will nearly double between 2023 and 2026 to reach roughly 96 GW globally, and that AI operations alone could potentially consume over 40% of that power. Deloitte also expects AI data centers’ annual power consumption to reach about 90 TWh by 2026, roughly one-seventh of a projected 681 TWh for all data centers globally.
The International Energy Agency puts global data center electricity consumption at about 415 TWh in 2024, around 1.5% of global electricity, rising to around 945 TWh, just under 3% of global electricity, in the IEA’s Base Case.
At that scale, data centers are no longer only IT infrastructure. They are energy infrastructure and a factor in national energy planning, grid resilience, and carbon accounting. Interconnection queues in several markets now extend for years, which means grid availability increasingly determines where a facility can be built rather than following from the decision.
Cooling at AI Density
As much as 40% of the power used in an AI data center is consumed by the systems built to keep those chips cool, rather than by the compute hardware itself. That makes thermal management the primary engineering constraint on high-density capacity.
Air cooling reaches its practical limit as density rises. For traditional enterprise densities, it remains highly effective, and for specific platforms, the air-cooled design is itself an advantage — the air-cooled Synopsys ZeBu emulation server is a case where customers value it directly. But as racks move into the upper end of the 30 to 100+ kW range, air alone stops being sufficient, and the industry has moved toward liquid cooling for the densest deployments.
Two approaches lead that transition. Direct-to-chip liquid cooling brings coolant to the components that generate the most heat through cold plates fitted to the package. Heat leaves at the source, and the rest of the server stays dry. Immersion cooling takes the opposite approach and places the whole server in a dielectric bath, so heat leaves uniformly across the rack, and fans and most air-handling equipment become unnecessary.
Both can be modeled and optimized before deployment using computational fluid dynamics and thermal analysis. For the cooling technologies and methods in depth, see What Is Data Center Cooling?
Sustainability and the Efficiency Question
Rapid capacity expansion creates tension with corporate and national sustainability commitments. A near-doubling of global data center electricity by 2030 would make the sector one of the fastest-growing sources of electricity demand. Large facilities can produce measurable local heat effects, and both direct water use for cooling and indirect water use for power generation are growing concerns.
Power usage effectiveness (total facility power divided by IT equipment power) remains the headline efficiency metric. A value of 1.0 would mean every watt entering the facility reaches computation, which is not physically achievable. Well-designed AI and HPC facilities target the low end of the scale; older facilities often sit well above it. The industry average has remained close to 1.55 to 1.59 since 2020, according to the Uptime Institute, and the gap between that average and what a purpose-built facility achieves is largely a design gap rather than an operational one.
That is the argument for closing it before construction. Retrofitting a live facility for an efficiency problem that a model would have surfaced is an expensive way to find it.
The Chip-to-Facility Stack
Chip-to-facility refers to the integrated engineering analysis stack that connects silicon-level simulation with facility-level multiphysics simulation: Synopsys silicon-level tools at the chip and package layer, and Ansys multiphysics solvers at the rack, room, and facility layer. It is not a standalone industry term. It is the framing used here to describe how the combined Synopsys and Ansys tools address the four engineering scales involved in AI facility design.
The reason the stack matters on this topic in particular is that AI facility constraints couple tightly. Performance, power, and thermal limits interact from the transistor through the rack to the building, and solving at one scale while ignoring the others produces bottlenecks, over-provisioning, or outright failures. The most common version of that mistake is optimizing the chip in isolation and then discovering the facility cannot cool it.
Figure 3. Four scales, and the direction analysis flows between them. Chip and package analysis establishes the heat source and the power map. Board and rack analysis carries it into the airflow model. Room and facility analysis completes the building picture. Operational models return measured behavior to inform the next design cycle.
Chip and Package
Every AI facility begins with the silicon inside it. The efficiency, power consumption, and thermal behavior of the whole installation are largely set at this scale, which makes chip design and IP selection a primary determinant of data center cost, scalability, and sustainability.
An AI chip must hit aggressive performance-per-watt targets inside die-size, packaging, thermal, and cost budgets, on a competitive schedule. The dominant challenge is data movement: energy is consumed largely by traffic between memory and compute, so designers maximize on-chip storage and data reuse. Heterogeneous compute integration and advanced-node scaling, where leakage and thermal effects intensify, compound it.
IP selection sits at the center of this risk equation. At leading-edge nodes, power, performance, area, and latency are defined as much by IP choice as by architecture, and reaching for a new interface standard or process node without silicon-proven IP raises re-spin exposure, where each iteration costs months and budget. Proven IP lets teams spend scarce engineering effort on differentiation — custom accelerators, system-level optimization — rather than on standard functionality. In practice, starting from proven IP can remove months from a schedule at a fraction of the cost of developing the same functionality in-house.
Verifying the design before fabrication is the other half of the problem. A modern AI chip carries tens of billions of transistors and must be validated for functional correctness, timing, power integrity, signal integrity, thermal behavior, and manufacturability — now one of the largest components of the development cycle, because an undetected bug surfaces as a re-spin. Multi-die designs and advanced packaging amplify this, since performance, power, and cooling must be optimized together across silicon, package, server, and rack. AI-powered electronic design automation with integrated multiphysics analysis is central to first-time silicon success.
The Synopsys IP portfolio covers logic libraries, embedded memories, I/O libraries, non-volatile memories, interface IP, security IP, and subsystems, all silicon-proven. IP Accelerated adds architecture design expertise, hardening, and signal and power integrity analysis to shorten IP integration and silicon bring-up.
Synopsys Fusion Design Platform carries a design from architectural exploration through to signoff. Fusion Compiler performs register-transfer-level to GDSII physical implementation for single-die designs, and 3DIC Compiler provides multi-die and advanced package co-design and optimization in a unified exploration-to-signoff platform.
At signoff, PrimeTime, PrimeShield, PrimeClosure, and IC Validator deliver static timing analysis, design robustness, design closure optimization, and physical verification respectively.
RedHawk-SC provides power integrity analysis, identifying voltage-drop hot spots and electromigration risks that would otherwise surface as in-field failures. Exalto delivers silicon-optimized electromagnetic modeling for signal and power integrity, where effects once negligible become first-order constraints at advanced nodes. PathFinder-SC handles electrostatic discharge reliability signoff, which matters more for parts operating near their thermal margins. RedHawk-SC is integrated with 3DIC Compiler, giving a continuous path for multi-die and advanced package co-design from exploration to signoff.
Board, Rack, and Room
Once the silicon exists, the problem becomes the systems and the building that house it. Ansys Icepak software provides electronics cooling analysis for components, boards, and enclosures, predicting the thermal behavior of racks and cooling configurations before hardware is built. Ansys Fluent software extends that to room and building scale, modeling airflow patterns, aisle containment, heating, ventilation and air conditioning (HVAC) behavior, and the behavior of liquid cooling deployments, including two-phase and immersion systems.
Ansys Mechanical software covers the structural side, including vibration, weight loading, and thermal expansion under sustained high-density operation, which becomes material as liquid-cooled racks approach a metric ton (2,200 lb). Ansys Sound software, part of the same Structures portfolio, predicts the acoustic noise a facility generates — increasingly a planning and permitting constraint for sites close to residential areas.
Facility and Operations
At facility scale, the questions are macro: site layout, power distribution, environmental footprint, and heat recovery. Ansys Discovery software supports early-stage assessment of layout and environmental impact. Ansys Maxwell software and Ansys Q3D Extractor software model electromagnetic fields and parasitic effects in busbars, cables, and power delivery networks at facility scale.
Heat rejected from a facility is conventionally lost to the atmosphere. Liquid cooling raises the return-water temperature enough to make that heat useful for district heating or industrial processes, and analysis is what determines whether the recovery loop is viable at a given site, where heat is generated, how it moves, and where it can be captured economically.
Ansys Twin Builder software compresses high-fidelity models into reduced-order models that execute fast enough for operational use, and Ansys TwinAI software combines that physics with measured data so a model recalibrates as equipment ages. On the silicon side, Silicon Lifecycle Management embeds on-chip monitors that track performance, reliability, and thermal behavior in service. Together, they close the loop between design intent and operating conditions.
Synopsys and Ansys Technologies for AI and HPC Data Centers
The technologies are grouped by the scale each one addresses.
| Group | Technologies | Function |
| Chip design and implementation | Fusion Compiler, DSO.ai, 3DIC Compiler, Multi-Die Design Solution | Register-transfer-level to layout implementation and AI-powered design space exploration, where power and thermal budgets are set |
| Verification and validation | VCS, ZeBu | Software simulation and hardware emulation for verifying complex chip designs and validating system-level hardware and software behavior |
| Chip power and thermal sign-off | RedHawk-SC, Exalto, PathFinder-SC | Voltage drop, electromagnetic behavior, electrothermal response, electrostatic discharge reliability |
| Silicon IP and in-field measurement | IP for HPC and data center SoCs, Silicon Lifecycle Management | High-performance, low-latency, power-efficient interface, foundation, and security IP; on-chip monitors reporting from the field |
| Facility analysis and operational twins | Ansys Icepak software, Fluent software, Mechanical software, Sound software, Discovery software, Maxwell software, Q3D Extractor software, Twin Builder software, TwinAI software | Thermal, structural, electromagnetic, acoustic, and fluid analysis from board to building, plus twin construction for operations |
Synopsys, Inc. (Nasdaq: SNPS) develops chip design, verification, and IP technologies at the silicon end of the stack. Ansys, part of Synopsys, develops multiphysics analysis and digital twin technologies at the facility end.
A note on the simulation-led approach in practice. Vertiv worked with Ansys to develop data center cooling systems using AI-enhanced optimization of heat exchanger coils and enterprise-wide simulation data management, evaluating design configurations virtually rather than prototyping each one physically.
Further Reading
- What Is a Data Center? — facility types, architecture, components, and how AI workloads have changed them
- What Is Data Center Cooling? — air, liquid, direct-to-chip, and immersion cooling compared
- What Is an AI Accelerator? — the silicon at the center of AI facility density
- What Is AI Chip Design? — how AI workloads change the chip design problem
- Meeting the Energy Demands of AI Data Centers — the energy challenge addressed from chip to facility
Explore AI and HPC Data Center Solutions
Designing and operating AI and HPC facilities requires engineering precision from the transistor to the building.
- Chip-level: The Synopsys HPC & Data Center Solution supports the development of the high-performance, power-efficient systems-on-chip that these workloads depend on.
- Facility-level: Ansys data center solutions address efficiency and resiliency through thermal, structural, and electromagnetic analysis.
Synopsys provides engineering solutions from silicon to systems.
Frequently Asked Questions
An AI and HPC data center — an AI facility of this kind is also widely known as an AI factory — is a facility purpose-built for artificial intelligence and high-performance computing workloads: model training, inference, scientific simulation, and the high-bandwidth data movement between them. It differs from a traditional facility in its silicon, which is accelerator-dense rather than general-purpose; its rack power density, which runs from 30 kW to over 100 kW rather than 5 to 15 kW; and its cooling, which is liquid rather than air at the densest deployments.
Closely related, and the terms are often used interchangeably, but the emphasis differs. An AI data center is the facility: the building, power infrastructure, cooling systems, and the accelerator-dense compute inside. An AI factory is that facility treated as a production system, built for the full model lifecycle of training, fine-tuning, and inference — the framing Nvidia introduced to describe a plant that manufactures intelligence from data and electricity rather than a building that stores servers. Every AI factory is an AI data center; not every AI data center runs the complete AI lifecycle that makes it one. The engineering constraints are the same either way: accelerator-dense racks, 30 kW to over 100 kW per rack, liquid cooling at the densest deployments, and power as the binding limit.
Per-facility consumption varies too widely with size and workload mix for a representative figure, so the useful numbers are aggregate. US data centers collectively consumed 76 TWh in 2018, 1.9% of US electricity; by 2028, the projection is 325 to 580 TWh, or 6.7 to 12% of national energy. At rack level, an accelerator-dense training rack draws from 30 kW to over 100 kW. Globally, Goldman Sachs Research projects data center power demand will grow 160% by 2030.
Air cooling remains effective at traditional enterprise densities, and for some platforms, an air-cooled design is a deliberate advantage. As rack density rises into the upper part of the 30 to 100+ kW range, air alone stops being sufficient. Direct-to-chip cooling brings coolant to the hottest components through cold plates fitted to the package; immersion cooling places the whole server in a dielectric bath. Both remove heat far more effectively than air, and both can be modeled in advance using Ansys Icepak and Ansys Fluent software.
Four dimensions. Silicon: accelerator-dense racks and custom systems-on-chip rather than general-purpose processors. Power density: 30 kW to over 100 kW per rack rather than 5 to 15 kW. Cooling: liquid at the densest deployments rather than air throughout. Workload profile: sustained parallel computation for training, inference, or simulation rather than a broad mix of enterprise applications, databases, and web services.
The silicon is the largest single determinant of a facility’s power and thermal profile. Because total facility power is IT power multiplied by power usage effectiveness, a watt removed at the chip removes the cooling and distribution overhead that would have supported it as well. Getting that right is an EDA and IP problem before it is a facility one: synthesis and place-and-route decisions set the power-performance-area envelope, power integrity and electrothermal sign-off catch the hot spots that would otherwise ship, and the choice of silicon-proven interface, foundation, and memory IP determines how much power the data movement between memory and compute costs — which is where most of a chip’s energy goes. Chips designed this way run cooler and draw less, and that saving compounds across every device in the facility.
Analysis locates constraints while they can still be designed out. At the chip, it establishes the power map and the heat source. At board and rack scale, it resolves where cooling actually reaches the load. At the facility scale, it addresses building airflow, structural loading, and heat recovery. After construction, reduced-order models carry the same physics into operational decisions.
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Architecting AI Factories: Rack-Scale Design Series
Agentic AI in Chip Design: Why Knowledge Becomes the Advantage (Part 3 of 4)
