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AI infrastructure requires more computing power, higher memory bandwidth, and greater energy efficiency. To meet those requirements, companies are increasingly turning to multi-die designs with advanced packaging.
Farhang Yazdani, CEO of BroadPak and a longtime leader in advanced semiconductor packaging, recently sat down with us to discuss the business tradeoffs, supply chain constraints, and system-level planning required for today’s multi-die designs.
His insights draw on BroadPak’s experience with real-world projects, including the practical design, manufacturing, and qualification challenges involved.
Farhang Yazdani, CEO, BroadPak
You’ve built BroadPak around the idea of designing chips beyond the die, at the system level. What convinced you that heterogeneous integration would become essential as monolithic scaling became more difficult?
BroadPak started in 2007, at the beginning of more complex packaging and integration. Even then, one attraction to multi-die designs was speed: in some cases, it was faster to bring a product to market by integrating components from different sources than by doing everything monolithically.
But early multi-chip-module designs also exposed challenges that were not obvious at first. Customers could manufacture and assemble a system, yet struggle to pass qualification because of mechanical stress, delamination, material behavior, or other reliability issues.
The industry learned early on that these are multiphysics challenges. Signal integrity and power integrity have to be addressed, along with thermal and mechanical stresses. The right materials and substrate design are important as well.
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Why is energy efficiency such a major driver now?
The upfront cost of a package is only one business consideration. Customers also have to consider how much energy the system can save over time. If a more expensive package brings components closer together and reduces the power required for communication, the operating savings can outweigh the higher initial cost.
As data center workloads grow, energy costs add up. The way a system is packaged — and how much data must travel between separate packages, across a board, or through higher-power I/O — can have a major impact on power consumption. Going to a smaller process node helps, but system architecture and packaging are becoming just as important. I/O is a major area we need to address.
What do customers find most difficult about multi-die design?
There are many challenges, but today I would say the biggest one is the supply chain.
Co-packaged optics, for example, depends on substrate and material availability, manufacturing capacity, and access to the right partners. When supply is constrained, customers may have to consider different options from the ones they initially preferred.
From a design perspective, the biggest challenge is managing system-level complexity. You have to account for the die, interconnects, power and thermal behavior, testing, and the manufacturing supply chain. Manufacturing also depends on having the right partner, the right expertise, and the right materials to assemble the product successfully.
Are companies achieving true system-level co-design today?
There is progress, but complete co-design across everything from the beginning is still more of a wish list.
What has changed is that customers are thinking about the package earlier. In the past, they often came to us after the die design, bump layout, and coordinates had already been finalized. Now, they engage before die design begins to discuss interposer needs, manufacturing, supply, and how the system can scale.
True co-design is easier when a single organization owns the system. But in the real world, chiplets and components may come from different suppliers, with different physical configurations and requirements.
It sounds like multi-die designs are still highly customized. How close is the industry to a true plug-and-play, multi-vendor chiplet ecosystem?
This is something that sounds good on the surface, but I think we are years from it.
There are standards for die-to-die communication, but further standardization is still needed in how chiplets communicate and in how we simplify the substrate and integration approach. The industry has embraced chiplets, but they work better today within a single organization that controls more of the design.
The broader vision of being able to source chiplets from different places and integrate them easily has been demonstrated, but the industry is not there yet at scale. It will come, but more slowly than many people expect.
In what ways can BroadPak and Synopsys make the biggest difference?
The opportunity is to bring system-level thinking into the design process earlier.
BroadPak helps customers address packaging architecture, implementation, manufacturing considerations, and the practical choices involved in bringing a multi-die product together. From the Synopsys perspective, it all comes back to system-level design and connectivity: the choice of EDA tools and IP.
The combination of electrical, mechanical, and thermal simulation is especially valuable. Ansys is the industry’s gold standard for simulating package behavior, including electrical, mechanical, and thermal effects and signal integrity. That combination is a proven path.
Reference designs and approaches that have already been simulated, manufactured, and tested are also helpful. They provide some of the groundwork for the decisions that need to be made. This is where the combined Synopsys and Ansys capabilities can provide significant value.
More broadly, customers need a more predictable, end-to-end way to evaluate whether a multi-die design can meet performance, power, reliability, manufacturability, and cost requirements before they commit to silicon.
What developments will shape the next phase of multi-die design?
The biggest breakthrough area I see is optical integration in packages, especially co-packaged optics. For disaggregation, CPO is a must.
As systems become more disaggregated and demand more bandwidth, electrical connectivity by itself can consume too much power. Bringing optical connectivity closer to the compute system can help lower power consumption and improve efficiency. We are also seeing developments such as polymer waveguides on organic substrates that could contribute to lower-power connectivity.
But co-packaged optics brings new challenges. You are dealing with photonic ICs, electrical ICs, die-to-die connectivity, hybrid bonding, laser sources, thermal management, mechanical stress, fine-pitch connections, reliability, and qualification. The supply chain is still developing as well.
What’s the most important thing engineering teams should keep in mind as they approach next-generation designs?
AI performance requires more than a high-end die. The substrate is becoming the fabric that connects compute, memory, power, and I/O. That fabric has to be co-designed from the start to meet performance, manufacturability, and reliability requirements.
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