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Key Takeaways
- Definition: Hardware-software co-design is the practice of designing a chip and the software that runs on it concurrently, rather than sequentially, so the complete system meets its performance, power, and latency targets.
- Core mechanism: Architectural decisions about the silicon are made with the software workload in view, and the software is modified and refined by the constraints of the hardware, with the two verified together before the chip is manufactured.
- Key differentiator: For Physical AI, co-design is what makes it possible to run multimodal perception and inference on a device within strict energy, latency, and thermal budgets.
- Primary value: Higher performance per watt, first-pass silicon success, faster time-to-market, and lower risk than a sequential design flow.
- Synopsys role: Synopsys provides tools across the co-design flow — architectural exploration, RTL and power optimization, AI-driven design-space optimization, 3D-IC design, and emulation — supporting engineering solutions from silicon to systems.
Definition
Hardware-software co-design is an engineering approach in which the design of the silicon and the software that needs to run on it is performed concurrently, with data and constraints exchanged between them. In a traditional flow, hardware and software are developed separately and integrated late in the design process. In a co-design flow, architectural decisions about the chip are made with the software workload in view, and the software is modified and refined by the constraints of the hardware. The goal is a system in which the two are matched closely enough to meet demanding performance and efficiency targets.
This approach matters most when a system has little margin, when it must deliver high computational throughput within a fixed power envelope, communicate at the target speed, and operate reliably. Physical AI systems sit squarely in that category. For a definition of the accelerators that co-design produces, see What Is an AI Accelerator?; this entry focuses on the co-design workflow that yields an efficient AI system-on-chip (SoC).
Why Physical AI Demands Co-Design
A Physical AI system must perceive its environment through multiple sensors, interpret numerous inputs, and act, often within milliseconds and often on battery power. Running large multimodal models on a device, rather than in the cloud, places the computation in proximity to the sensors and actuators, which reduces latency but concentrates the demand for efficient processing on the chip itself. Three constraints make this difficult and make co-design necessary.
| Constraint | Why it is hard for Physical AI | Co-design response |
| Performance per watt | Mobile systems carry their own power, so the useful measure is throughput within a power budget (TOPS per watt), not raw throughput. | Optimize power alongside architecture from the start |
| Latency | Signals must travel between sensors, compute, and actuators fast enough for real-time action. | Match the accelerator and memory architecture to the workload |
| Thermal and physical limits | Efficient silicon runs cooler and fits the size and weight limits of a physical device. | Power integrity and thermal-aware signoff |
General-purpose processors rarely meet all three at once. Meeting them calls for specialized silicon such as neural processing units (NPUs) and AI accelerator IP, designed in concert with the software it will run. The demands that multimodal Physical AI places on next-generation NPUs are examined in Why Next-Generation NPUs Are Essential for Physical AI.
Figure 1 — The Three Constraints. A Physical AI SoC must satisfy performance per watt, latency, and thermal limits at the same time. Optimizing any one in isolation tends to compromise the others, which is why hardware and software are designed together rather than sequentially.
The Co-Design Workflow
Co-design for a Physical AI SoC brings the hardware and software views together at each stage of the flow. Synopsys, Inc. (Nasdaq: SNPS) provides tools used across all stages of design, signoff, and verification.
Figure 2 — The Co-Design Workflow. Four stages inform one another: architectural exploration sets the structure against the target workload; power and performance optimization keeps the design within budget; AI-driven optimization searches the design space; and integration and verification confirm hardware and software behave correctly together before tape-out. The dashed feedback arrow shows the iterative nature — findings at any stage can revise earlier decisions.
1. Architectural Exploration
Co-design begins before any register-transfer-level (RTL) code is written, by evaluating candidate architectures against the target workload. Synopsys Platform Architect supports early exploration of processor, memory, and interconnect choices, so architects can see how a design will handle the intended AI workload and where bottlenecks (often memory bandwidth) will appear. Synopsys RTL Architect performs early architectural exploration and optimization and analyzes and optimizes the RTL for power, performance, area (PPA), and congestion impacts.
2. Power and Performance Optimization
Because performance per watt is the governing constraint, power is analyzed and optimized early rather than checked at the end. Synopsys SpyGlass Power evaluates and reduces power at the RTL stage, and Synopsys RedHawk-SC provides power integrity signoff later in the flow. Synopsys PrimePower delivers a comprehensive, physically aware, and signoff-accurate power analysis solution that spans early RTL exploration to final gate-level signoff, and Synopsys Fusion Compiler carries power-aware synthesis and physical implementation through to layout. Optimizing power at multiple stages keeps the design within its budget as it matures.
3. AI-Driven Design Optimization
Design-space exploration can itself be accelerated with AI. Synopsys DSO.ai applies machine learning to search the design space for better power, performance, and area outcomes than manual iteration typically finds within the same schedule. Synopsys 3DIC Compiler addresses the unique challenges of 3D IC design by providing a unified, scalable, and automated environment that integrates chip and package co-design, enabling improved power, performance, area (PPA), and faster time to market for complex multi-die designs.
4. Integration and Verification
The accelerator and the surrounding SoC must be integrated tightly, and the hardware and software verified together before silicon exists. Synopsys ZeBu emulation systems let teams run real software workloads against the hardware design early, so that hardware and software meet long before tape-out. Running production software against the design before any silicon exists means working with an electronics digital twin, a virtual replica of the electronic hardware used during the design phase, but applicable throughout the life cycle. The accelerator is integrated alongside the interface, foundation, and security IP that a complete SoC requires.
Key Technologies in the Co-Design Flow
Each stage of the flow depends on tools with a distinct function. Grouping them by function, rather than by where they appear in a schedule, clarifies what each contributes.
| Stage / function | What it does | Synopsys technology |
| Architectural exploration | Evaluate architectures against the AI workload; optimize RTL for PPA and congestion | Platform Architect, RTL Architect |
| RTL power analysis | Reduce power early, at the RTL stage | SpyGlass Power |
| Power analysis and signoff | Physically aware power analysis from RTL to gate-level signoff | PrimePower |
| Power integrity signoff | Confirm power delivery late in the flow | RedHawk-SC |
| Synthesis and implementation | Power-aware synthesis through to layout | Fusion Compiler |
| AI-driven design-space optimization | Search for better power, performance, and area | DSO.ai |
| 3D-IC design | Integrate chip and package co-design for multi-die | 3DIC Compiler |
| Hardware-software verification | Run software on the design before silicon | ZeBu emulation |
Co-Design in Practice
The value of co-design is apparent in production silicon. When the edge-AI company SiMa.ai designed its second-generation Modalix SoC for multimodal Physical AI, it ran the complete design-to-tape-out flow in-house using Synopsys tools and IP, and reached bug-free first-pass (A0) silicon. SiMa.ai states that Modalix delivers “10 times the performance per watt of alternatives” and, configured as a four-chip cluster, “up to 200 TOPS.”
The team credited early hardware-software integration on emulation. “Using ZeBu, we were able to run Llama model workloads even before the chip arrived, and that helped us gain confidence in the health of the design and maturity of the software,” said Srivi Dhruvanarayan, SiMa.ai vice president of hardware engineering. The full account is in the SiMa.ai customer story.
Co-Design vs. Traditional Sequential Design
The difference between co-design and a traditional sequential flow is clearest when set side by side.
| Dimension | Traditional sequential design | Hardware-software co-design |
| Order of work | Hardware first, software after silicon | Hardware and software developed together |
| When integration happens | Late, after tape-out | Early, on emulation and virtual models |
| Power optimization | Checked near the end | Optimized from architecture onward |
| Risk of respins | Higher, issues surface after fabrication | Lower, issues surface pre-silicon |
| Fit for Physical AI budgets | Difficult to achieve performance-per-watt targets | Designed to achieve them |
Figure 3 — Co-Design vs. Sequential Design. In the sequential timeline, software integration waits for silicon, and issues surface late and expensively. In the co-design timeline, hardware and software proceed in parallel and meet early on emulation, so problems are found and fixed before tape-out. The co-design timeline is highlighted as the path that meets Physical AI budgets.
Key Benefits of Hardware-Software Co-Design
Higher Performance per Watt
Designing silicon and software together lets a system achieve the TOPS-per-watt targets that mobile Physical AI depends on, targets a general-purpose approach struggles to reach.
First-Pass Silicon Success
Verifying hardware and software together before tape-out reduces the risk of a respin, which can cost millions of dollars and add months to a schedule.
Faster Time-to-Market
Developing hardware and software in parallel, rather than in sequence, compresses the overall program.
Lower Development Risk
Surfacing integration issues early, on emulation and virtual models, means they are found while they are still inexpensive to fix.
Industry Applications
| Industry | Where co-design matters | Example |
| Automotive | ADAS and autonomous-driving SoCs under safety and power constraints | Perception and inference silicon co-designed with the software stack |
| Robotics | On-device inference for perception and control | Efficient accelerators matched to robotics workloads |
| Edge AI devices | Always-on perception within tight power budgets | Smart cameras and sensors running multimodal models locally |
| Drones and UAVs | Low-weight, low-power autonomy | Flight and navigation compute co-designed for efficiency |
Engineering Challenges
System Complexity
Co-designing hardware and software increases the number of interacting decisions, which demands disciplined architecture and cross-team collaboration.
Tool and IP Integration
An efficient SoC integrates accelerator, interface, foundation, and security IP that must work together; integration that benefits from a consistent toolchain.
Memory Bandwidth
Large AI models are frequently memory-bound; providing enough bandwidth without exceeding the power budget is a central co-design challenge.
Hardware-Software Verification Effort
Verifying that hardware and software behave correctly together, before silicon, requires emulation and virtual-model infrastructure and the effort to build representative test workloads.
Frequently Asked Questions
Hardware-software co-design is the practice of designing a chip and the software that runs on it concurrently, so the complete system meets its performance, power, and latency targets. It replaces a sequential flow in which hardware and software are developed separately and integrated late in the design process.
Physical AI systems must run demanding AI workloads on a device within strict power, latency, and thermal constraints. Designing silicon and software together lets engineers match the two closely enough to meet those constraints, which a sequential flow rarely achieves.
A neural processing unit (NPU) is specialized silicon that executes AI inference far more efficiently than a general-purpose processor. In an AI SoC, it handles the perception and inference workload, which is what allows a Physical AI device to process sensor data in real time within its power budget.
TOPS per watt measures how many tera operations per second a chip delivers for each watt of power it consumes. For mobile Physical AI systems that carry their own power, this efficiency measure matters more than raw throughput, because it determines both battery life and thermal behavior.
Emulation lets a team run real software workloads against the hardware design before the chip is manufactured. This early integration surfaces performance and power issues while they are still inexpensive to fix and builds confidence that hardware and software will work together at tape-out.
In traditional design, hardware is completed first, and software is integrated after silicon is available, so integration issues surface late. In co-design, hardware and software are developed in parallel and verified together early, which lowers the risk of respins and helps meet tight efficiency targets.
Common categories include architectural exploration (Synopsys Platform Architect, RTL Architect), RTL and power optimization (SpyGlass Power, PrimePower, Fusion Compiler), power integrity signoff (RedHawk-SC), AI-driven design-space optimization (DSO.ai), 3D-IC design (3DIC Compiler), and emulation for hardware-software verification (ZeBu).
No. Co-design shifts much of the integration and verification effort to virtual models and emulation before silicon, but final validation still requires physical hardware, particularly for safety-critical products.
Explore Synopsys IP and Design Solutions
Building an efficient Physical AI SoC depends on matching silicon and software across the design flow. Learn more about Synopsys IP and design solutions for AI SoCs.
Further Reading
- What Is Physical AI? — the broader engineering context for this topic.
- Why Next-Generation NPUs Are Essential for Physical AI — how NPU architecture must evolve for multimodal Physical AI.
- From Concept to Tape-Out: SiMa.ai Achieves Bug-Free A0 Silicon for Physical AI — a production hardware-software co-design case study.
- From Tokens to Physics: How Neuromorphic Computing Will Power Physical AI — emerging low-power edge architectures.
- Architecting Physical AI SoCs with Standards-Based IP — on-demand webinar on interface IP for Physical AI SoCs.
- What Is an Electronics Digital Twin? — the design-phase virtualization behind pre-silicon hardware-software verification.
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