Download Brochure
Contact Us
Contact Us
Contact Us
  • Software Integrity
  • Tools
  • Services
  • Training
  • Solutions
  • Resources
  • Customers
  • Partners
  • Blog
Contact Sales
  • Company
  • About Us
  • Investor Relations
  • Community
  • Newsroom
  • Resources
  • Careers
Contact Us
All Synopsys
+ Silicon Design & Verification + Silicon IP + Software Integrity + About Us
Support
SolvNet Software Integrity Customer Community
Global SItes
日本サイ ト 中文网站 中文網站 Сайт Россия Deutsche Webseite

SNUG Austin 2016 Proceedings

2018 | 2017 | 2016 | 2015 | 2014

Complete Proceedings

User Papers and Presentations
TA1 Low Power Optimization and Checking
Black-Boxing Techniques for Improving VC-LP Throughput (2nd Place - Best Presentation)
Author(s): Parag Mandrekar, Joseph Gutierrez, Hank Lin - Advanced Micro Devices; Vishwanath Sundararaman - Synopsys
PaperPresentation
TA3 Testbench Best Practices
Applying Stimulus and Sampling Outputs - UVM Verification Testing Techniques
Author(s): Clifford E. Cummings - Sunburst Design
PaperPresentationSession Recording

Complex Constraints: Unleashing the Power of the VCS SystemVerilog Constraint Solver (Technical Committee Award)
Author(s): John Dickol - Samsung
PaperPresentationSession Recording

Configuring a Date with a Model - A Guide to Configuration Objects and Register Models
Author(s): Jeff Montesano, Jeff Vance - Verilab
PaperPresentationSession Recording
TA4 Simulation, Advanced Usage, and Debug
Advanced X-Prop Usage for the NXP LS1088A Verification
Author(s): Jie Wen, Amol Bhinge, Vaibhav Kumar - NXP Semiconductors; Jiri Prevratil - Synopsys
PaperPresentationSession Recording

SystemVerilog: Reusable Class Features and Safe Initialization of Static Variables
Author(s): Will Adams - Advanced Micro Devices
PaperPresentation

Tough Bugs vs. Smart Tools - L2/L3 Cache Verification Using System Verilog, UVM, and Verdi Transaction Debugging
Author(s): Vibarajan Viswanathan, Doug Reed - Centaur Technology; Juliet Runhaar, Jun Zhao - Synopsys
PaperPresentation
TA5 Prototyping
High-Level Performance Estimation on Virtual Prototypes Employing Timing Annotation
Author(s): Barry Spotts, Robert Kaye - ARM
PaperPresentation

Latch-Based CPU Prototyping with HAPS Platform
Author(s): Mark Nadon - Synopsys
PaperPresentation
TB3 Testbench Quality and Formal Verification
Unique Methodology to Streamline the Checking of Design Tie-Offs (3rd Place - Best Presentation)
Author(s): Varun Ramesh, Amol Bhinge - NXP Semiconductors; Jay Dutt - Synopsys
PaperPresentationSession Recording
TB4 Functional Coverage and Testbench Considerations
Molding Functional Coverage and Reporting for Highly Configurable IP
Author(s): Jeremy Ridgeway, Kavitha Chaturvedula - Broadcom
PaperPresentation
TB5 Characterization
Power-Intent Verification Methodology in Multi-Voltage Domain Custom Memory Macro to Prevent Circuit Failures
Author(s): Amlan Ghosh, Keith Kasprak - Advanced Micro Devices; Dave Hedges - Synopsys
PaperPresentationSession Recording

Statistical Characterization Methodology to Design and Margin for 16nm FinFET Flops
Author(s): Savithri Sundareswaran - NXP Semiconductors
PaperPresentation
TB6 DFTMAX Ultra Applications
DFTMAX Ultra User Experience for Small, Digital, Mixed-Signal Devices (1st Place - Best Presentation)
Author(s): Christopher Ryan, Kien Vi - Maxim Integrated
PaperPresentationSession Recording

Low-Power DFT and Effective Test Pattern Count Reduction in a Custom High-Performance Applications Processor Design
Author(s): Vivek Ramnath, Kelvin Ge, Padma Rayapureddy - Samsung; Surya Duggirala - Synopsys
PaperPresentationSession Recording
TC3 Formal Verification
The Lights in the Tunnel: Coverage Analysis for Formal Verification
Author(s): Xiushan Feng - Oracle; Abhishek Muchandikar, Xiaolin Chen - Synopsys
PaperPresentationSession Recording

Using Formal Tools to Verify Datapath Designs During Various Phases of a Processor Development
Author(s): Sankar Gurumurthy, Farhan Rahman - Advanced Micro Devices; Ankit Saxena, Ashutosh Prasad - Oski Technology
PaperPresentationSession Recording

Verifying Microprocessor Debug-Bus Connectivity Formally Using VC Formal
Author(s): Vinayak Kamath - Advanced Micro Devices; Xiaolin Chen - Synopsys
PaperPresentationSession Recording
TC4 Testbench Quality and Reuse
Advanced Verification Techniques for the NXP LS1088A Memory Validation
Author(s): Aditya Musunuri, Amol Bhinge - NXP Semiconductors; Nasib Naser - Synopsys
PaperPresentationSession Recording

Layered Testbench Architecture for Serial Protocol Using UVM
Author(s): Gaurav Brahmbhatt, Pinal Patel, Gaurang Chitroda, Manish Patel - eInfochips; Joe McCann - Synopsys
PaperPresentationSession Recording

Leveraging LevelDB for Unit-Level Replay of Top-Level Stimulus in UVM
Author(s): Nick Jones - Samsung
PaperPresentationSession Recording
Publication Only
Detoxify Your Schedule With A Low-Fat UVM Environment
Author(s): Nihar Shah - Oracle Labs
Publish Only

Early Design decisions based on RTL Power Estimation
Author(s): Sandilya Bhamidipati - NXP, Rose Wang - NXP
Publish Only

Effective SystemVerilog Functional Coverage: Design and Coding Recommendations
Author(s): Vanessa Cooper, Jonathan Bromley, Mark Litterick - Verilab
Publish Only

Executable Verification Plan (XVP)
Author(s): Gaurav Brahmbhatt, Gaurang Chitroda, Manish Patel, Pinal Patel - eInfochips; Joe McCann - Synopsys
Publish Only

Non-DMSA Multi-Scenario ECO Guidance with PrimeTime
Author(s): Curt Banks - Maxim Integrated, Jinwei Tioh - Maxim Integrated
Publish Only
Tutorials
TA1 Low Power Optimization and Checking
Improving Timing and Power with PrimeTime ECO Flows
Author(s): Troy Epperly - Synopsys
TutorialVideo
TA2 IC Compiler II: ARM® Cortex®-A73 Implementation and Large Block Floorplanning
Floorplanning Large Blocks Using IC Compiler II
Author(s): David Peart - Synopsys
TutorialVideo
TA5 Prototyping
Accelerate Your Prototyping Productivity Leveraging HAPS Integrated Prototyping Solution
Author(s): Kris Dobecki, Bob Efram, Ajay Jagtiani - Synopsys
TutorialVideo
TA6 Synopsys Automotive Test Solution: Moving the DFT Needle Forward
Synopsys Automotive Test Solution: Moving the DFT Needle Forward
Author(s): Adam Cron - Synopsys
TutorialVideo
TB1 Synthesis and Advanced STA Reporting
Design Compiler Update and Runtime Best Practices
Author(s): Joseph Dang - Synopsys
TutorialVideo

Effective Reporting and Analysis of Timing Results with PrimeTime
Author(s): David Peterson - Synopsys
TutorialVideo
TB2 IC Compiler II Best Practices: High Performance GPUs and In-Design IC Validator
Best Practices for a Performance- and Area-Focused Implementation of High-Performance GPUs Using Galaxy Design Platform
Author(s): Daniel Biset - Synopsys
TutorialVideo

Updates and Best Practices for IC Compiler II with In-Design IC Validator
Author(s): Chris Grossmann - Synopsys
TutorialVideo
TB3 Testbench Quality and Formal Verification
Essential Ingredients of Formal Based Verification
Author(s): Anders Nordstrom - Synopsys
TutorialVideo
TB4 Functional Coverage and Testbench Considerations
Unified Verification Planning and Coverage
Author(s): David Lee - Synopsys
Tutorial
TB6 DFTMAX Ultra Applications
DFTMAX Ultra: Achieve Additional Cost Reduction with Hardware-Assisted Shift Power Reduction
Author(s): Adam Cron - Synopsys
TutorialVideo
TC1 Functional ECO Implementation and Static Checking
ECO User Case Studies Using Formality Ultra
Author(s): David Yatim - Synopsys
TutorialVideo

Static Analysis with SpyGlass
Author(s): Russell Roan - Synopsys
TutorialVideo
TC2 Implementation Best Practices and Advanced Techniques
Implementing a 150M+ Instance Networking Chip at 28nm with Galaxy Platform
Author(s): Indira Velamuri - Synopsys
TutorialVideo
TC5 Custom Layout and Simulation Environment
Custom Compiler Technology Walkthrough
Author(s): Graham Etchells, Narendra Shenoy - Synopsys
TutorialVideo
TC6 TetraMAX II and SpyGlass
Connectivity Validation with SpyGlass
Author(s): Al Joseph - Synopsys
TutorialVideo

TetraMAX II ATPG, Broadcom's Results and Experience
Author(s): Lori Schramm - Synopsys; Ken Posse - Broadcom
Tutorial

TetraMAX II: Reduce Test Cost by 25 Percent with 10X Faster Runtime
Author(s): Adam Cron - Synopsys
TutorialVideo
Demo
TC5 Custom Layout and Simulation Environment
Walk-Through of SAE: The New Simulation Analysis Environment in the Latest Release of HSPICE, FineSim, and CustomSim
Author(s): Brian Chen - Synopsys
TutorialVideo
User Presentation
TA2 IC Compiler II: ARM® Cortex®-A73 Implementation and Large Block Floorplanning
Best Practices for High-Performance, Energy-Efficient Implementations of the ARM Cortex-A73 Processor in 16-nm FinFET Plus (16FF+) Process Technology Using Synopsys Galaxy Design Platform
Author(s): Nandan Nayampally - ARM; Michael Montana - Synopsys
PresentationVideo
TC2 Implementation Best Practices and Advanced Techniques
Achieving Correlation Between Synthesis and Routed Design for High-Performance Block
Author(s): Umesh Chejara - Advanced Micro Devices
PresentationVideo

Structural MSCTS Implementation Best Practices
Author(s): Trenton Henrichson - Advanced Micro Devices
PresentationVideo

September 11, 2019
Register Now!

View All SNUG Proceedings

View past keynotes from SNUG Silicon Valley

Contact Us

Platinum Sponsors:

Arm
GLOBALFOUNDRIES
Samsung
tsmc
Related Items