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| User Papers and Presentations |
| TA1 Low Power Optimization and Checking |
Black-Boxing Techniques for Improving VC-LP Throughput (2nd Place - Best Presentation)
Author(s): Parag Mandrekar, Joseph Gutierrez, Hank Lin - Advanced Micro Devices; Vishwanath Sundararaman - Synopsys |
|
| TA3 Testbench Best Practices |
Applying Stimulus and Sampling Outputs - UVM Verification Testing Techniques
Author(s): Clifford E. Cummings - Sunburst Design |
|
Complex Constraints: Unleashing the Power of the VCS SystemVerilog Constraint Solver (Technical Committee Award)
Author(s): John Dickol - Samsung |
|
Configuring a Date with a Model - A Guide to Configuration Objects and Register Models
Author(s): Jeff Montesano, Jeff Vance - Verilab |
|
| TA4 Simulation, Advanced Usage, and Debug |
Advanced X-Prop Usage for the NXP LS1088A Verification
Author(s): Jie Wen, Amol Bhinge, Vaibhav Kumar - NXP Semiconductors; Jiri Prevratil - Synopsys |
|
SystemVerilog: Reusable Class Features and Safe Initialization of Static Variables
Author(s): Will Adams - Advanced Micro Devices |
|
Tough Bugs vs. Smart Tools - L2/L3 Cache Verification Using System Verilog, UVM, and Verdi Transaction Debugging
Author(s): Vibarajan Viswanathan, Doug Reed - Centaur Technology; Juliet Runhaar, Jun Zhao - Synopsys |
|
| TA5 Prototyping |
High-Level Performance Estimation on Virtual Prototypes Employing Timing Annotation
Author(s): Barry Spotts, Robert Kaye - ARM |
|
Latch-Based CPU Prototyping with HAPS Platform
Author(s): Mark Nadon - Synopsys |
|
| TB3 Testbench Quality and Formal Verification |
Unique Methodology to Streamline the Checking of Design Tie-Offs (3rd Place - Best Presentation)
Author(s): Varun Ramesh, Amol Bhinge - NXP Semiconductors; Jay Dutt - Synopsys |
|
| TB4 Functional Coverage and Testbench Considerations |
Molding Functional Coverage and Reporting for Highly Configurable IP
Author(s): Jeremy Ridgeway, Kavitha Chaturvedula - Broadcom |
|
| TB5 Characterization |
Power-Intent Verification Methodology in Multi-Voltage Domain Custom Memory Macro to Prevent Circuit Failures
Author(s): Amlan Ghosh, Keith Kasprak - Advanced Micro Devices; Dave Hedges - Synopsys |
|
Statistical Characterization Methodology to Design and Margin for 16nm FinFET Flops
Author(s): Savithri Sundareswaran - NXP Semiconductors |
|
| TB6 DFTMAX Ultra Applications |
DFTMAX Ultra User Experience for Small, Digital, Mixed-Signal Devices (1st Place - Best Presentation)
Author(s): Christopher Ryan, Kien Vi - Maxim Integrated |
|
Low-Power DFT and Effective Test Pattern Count Reduction in a Custom High-Performance Applications Processor Design
Author(s): Vivek Ramnath, Kelvin Ge, Padma Rayapureddy - Samsung; Surya Duggirala - Synopsys |
|
| TC3 Formal Verification |
The Lights in the Tunnel: Coverage Analysis for Formal Verification
Author(s): Xiushan Feng - Oracle; Abhishek Muchandikar, Xiaolin Chen - Synopsys |
|
Using Formal Tools to Verify Datapath Designs During Various Phases of a Processor Development
Author(s): Sankar Gurumurthy, Farhan Rahman - Advanced Micro Devices; Ankit Saxena, Ashutosh Prasad - Oski Technology |
|
Verifying Microprocessor Debug-Bus Connectivity Formally Using VC Formal
Author(s): Vinayak Kamath - Advanced Micro Devices; Xiaolin Chen - Synopsys |
|
| TC4 Testbench Quality and Reuse |
Advanced Verification Techniques for the NXP LS1088A Memory Validation
Author(s): Aditya Musunuri, Amol Bhinge - NXP Semiconductors; Nasib Naser - Synopsys |
|
Layered Testbench Architecture for Serial Protocol Using UVM
Author(s): Gaurav Brahmbhatt, Pinal Patel, Gaurang Chitroda, Manish Patel - eInfochips; Joe McCann - Synopsys |
|
Leveraging LevelDB for Unit-Level Replay of Top-Level Stimulus in UVM
Author(s): Nick Jones - Samsung |
