SNUG Austin 2014 Proceedings

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Complete Proceedings


User Papers and Presentations
FA1 - User & Tutorial Session - Improving DC QoR and Golden UPF
FA1.1 - Sequential Logic Duplication for Front-End Design
Author(s): Christopher Stites - Advanced Micro Devices
PaperPresentation

FA1.2 - Front-End Method for IO Port Constraint Optimization and Convergence
Author(s): Brian Walters, Christopher Stites - Advanced Micro Devices
PaperPresentation

FA2 User & Tutorial Session - Top Level Implementation, Physically Aware PT-ECO, 16nm FinFET Flow
FA2.2 - Top Level Design Closure Made Easy
Author(s): Bijoy James - Altera Corporation
PaperPresentation

FA4 - User & Tutorial Session - FPGA Prototyping
FA4.3 - Test IP - Bringing the Tools and Methodology from Pre-Silicon Verification to Post-Silicon Validation
Author(s): Al Czamara, Richard Proto, Paul Tomashevskyi - Test Evolution
PaperPresentationSession Recording

FA5 - User Session - NanoTime for SRAM and Cross Talk Noise; Silicon Smart POCV Characterization
FA5.1 - Embedded SRAM Analysis and Characterization Using NanoTime for Memories
Author(s): Robert Murray - NVIDIA; Felipe R. Schneider - Synopsys, Inc.
PaperPresentation

FA5.2 - A Complete Static Crosstalk Noise Analysis Flow Using NanoTime
Author(s): Stephen Lim, David Newmark - Advanced Micro Devices; Frank Yang, Maureen Ladd - Synopsys, Inc.
PaperPresentation

FA5.3 - Parametric On-Chip Variation (POCV) Characterization with SiliconSmart
Author(s): Lyren Brown, David Newmark - Advanced Micro Devices; Myles Prather - Synopsys, Inc.
PaperPresentation

FB1 - User & Tutorial Session - Placement-Aware Multibit Register and Fomality Ultra
FB1.1 - Using the New Placement-Aware Multibit Register Mapping in Design Compiler Graphical
Author(s): Ken Umino, Hyon Han - Samsung Advanced Research Center; LaMark Chance, Sharrone Smith - Synopsys, Inc.
PaperPresentation

FB2 - User & Tutorial Session - Lynx Design System and ICC II Product Walkthrough
FB2.2 - IC Compiler II and the Power of 10x - A Product Walk-Through
Author(s): JC Lin, Ashwini Mulgaonkar - Synopsys, Inc.

FB3 - User Session - Techniques for Smarter Verification
FB3.1 - Handling Windows of Uncertainty - Reducing False Errors from Variable DUT Timing
Author(s): Jeffery Vance - Verilab
PaperPresentationSession Recording

FB3.2 - Reality and Challenges in Using Save/Restore in SoC Verification Environment (2nd Place - Best Presentation)
Author(s): Satish Naidu, Amol Bhinge - Freescale Semiconductor
PaperPresentationSession Recording

FB4 - User & Tutorial Session - Formal Made Easy, Test Quality
FB4.2 - How Do You Know When Your Test Is Broken? Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions
Author(s): Kelly D. Larson - Paradigm Works
PaperPresentation

FB5 - User Session - Test Power - Problems & Solutions
FB5.1 - ATPG Techniques and Methodology for Low-Power High Effectiveness Pattern Generation in a High Performance Quad-Core CPU Design (Best Paper Award, Technical Committee Award)
Author(s): Kelvin Ge, Vivek Ramnath - Samsung Electronics
PaperPresentationSession Recording

FB5.2 - Low Power Shift - Analysis and Design (2nd Place - Best Presentation)
Author(s): Michelle Vallabhanath, Naveen Mysore, Stefano Zanatta - Avago Technologies
PaperPresentation

FC1 - User & Tutorial Session - Advanced PT - Hyperscale & Physically Aware ECO and DC 2014.09 Highlights
FC1.1 - Hierarchical Timing Analysis using PrimeTime HyperScale for Complex SoCs (3rd Place - Best Presentation)
Author(s): Erik Gonzalez, Ilana Shternshain, Mahesh Sharma - Advanced Micro Devices
PaperPresentation

FC2 - User & Tutorial Session - High Performance Block Design, ICC 2014.09 Update Training, 700M Gate SoC Implementation Lynx Design Flow, High Performance Block Design, ICC 2014.09 Update Training
FC2.1 - Design of a High-Speed Data Interface Using Synopsys Toolset
Author(s): Rahul Bhargava, Umesh Chejara, Michael Quimby - Advanced Micro Devices
PaperPresentation

FC3 - User & Tutorial Session - UVM Messages, Comprehensive Debug, Verifying LTSSMs
FC3.1 - UVM Message Display Commands Capabilities, Proper Usage, and Guidelines (1st Place - Best Presentation)
Author(s): Clifford E. Cummings - Sunburst Design, Inc.
PaperPresentation

FC3.3 - Whitebox Approach for Verifying PCIe Link Training and Status State Machine
Author(s): Pinal Patel, Gaurang Chitroda - eInfochips; Colm McSweeney, Joe McCann - Synopsys, Inc.
PaperPresentation

FC4 - User & Tutorial Session - Customizing Debug, Certitude for Connectivity Checking
FC4.2 - Dynamically Configured Java Based Register Windows for Efficient Simulation Debug
Author(s): Dan Helm - ARM
PaperPresentation

FC4.3 - Using Certitude in SoC Connectivity Checking Flow
Author(s): Ross Patterson, Carmen Vargas - Freescale Semiconductor
PaperPresentation

Tutorials
FA1 - User & Tutorial Session - Improving DC QoR and Golden UPF
FA1.3 - UPF Refinement – Considerations and Application
Author(s): Josefina Hobbs - Synopsys, Inc.
Tutorial

FA2 User & Tutorial Session - Top Level Implementation, Physically Aware PT-ECO, 16nm FinFET Flow
FA2.1- Integrated Tool Flow Certification for N16FinFET Design
Author(s): Guru Prasad - TSMC

FA2.3 - PrimeTime ECO - Now Physically Aware
Author(s): Troy Epperly - Synopsys, Inc.
TutorialVideo

FA4 - User & Tutorial Session - FPGA Prototyping
FA4.2 - Integrating Siloti into Live FPGA Debug
Author(s): Kris Dobecki - Synopsys, Inc.
TutorialVideo

FB1 - User & Tutorial Session - Placement-Aware Multibit Register and Fomality Ultra
FB1.2 - Functional ECOs Made Easier with Formality Ultra
Author(s): Steve Lamb - Synopsys, Inc.
TutorialVideo

FB4 - User & Tutorial Session - Formal Made Easy, Test Quality
FB4.1 - From Formal Apps to End-to-End Verification - Formal Analysis for Everyone!
Author(s): Vigyan Singhal - Oski Technologies; Anders Nordstrom - Synopsys, Inc.
Tutorial

FC1 - User & Tutorial Session - Advanced PT - Hyperscale & Physically Aware ECO and DC 2014.09 Highlights
FC1.2 - PrimeTime ECO - Now Physically Aware
Author(s): Troy Epperly - Synopsys, Inc.
Tutorial

FC1.3 - Design Compiler 2014.09 Release Highlights
Author(s): Joseph Dang - Synopsys, Inc.

FC2 - User & Tutorial Session - High Performance Block Design, ICC 2014.09 Update Training, 700M Gate SoC Implementation Lynx Design Flow, High Performance Block Design, ICC 2014.09 Update Training
FC2.2 - IC Compiler J-2014.09 Release Highlights
Author(s): Frank Gover - Synopsys, Inc.
Video

FC3 - User & Tutorial Session - UVM Messages, Comprehensive Debug, Verifying LTSSMs
FC3.2 - Going Beyond the Waveform: 10 Things You Probably Didn't Know Verdi Could Do
Author(s): Jiri Prevratil - Synopsys, Inc.
Tutorial

FC4 - User & Tutorial Session - Customizing Debug, Certitude for Connectivity Checking
FC4.1 - Increase Your Debug Productivity with VC Apps
Author(s): Brian Schneider - Synopsys, Inc.
Tutorial

FC5 - Tutorial Session - Reducing the Time, Effort, Power, and Cost of Quality SoC Testing
FC5.1 - Reducing the Time, Effort and Cost of Quality SoC Testing
Author(s): Adam Cron - Synopsys, Inc.
TutorialVideo

Vision Session
FA3 Synopsys Verification
FA3.1 - Synopsys Verification - Looking Ahead to Faster Time-to-Market
Author(s): Synopsys, Inc.
Tutorial Tutorial

Workshop
FA6 - Workshop: Enabling SoC Implementation
FA6.1 - IC Compiler and Galaxy Custom Router Workshop
Author(s): Chris Shaw - Synopsys, Inc.

FB6 - Workshop: Enabling SoC Implementation
FB6.1 - IC Compiler and Galaxy Custom Router Workshop
Author(s): Chris Shaw - Synopsys, Inc.

User Presentation
FA4 - User & Tutorial Session - FPGA Prototyping
FA4.1 - Getting Results with Xilinx's Stacked Silicon Interconnect Devices
Author(s): Rich Wiegard - Xilinx, Inc.
PresentationVideo

FB2 - User & Tutorial Session - Lynx Design System and ICC II Product Walkthrough
FB2.1 - Leveraging the Lynx Design System
Author(s): Steve Cline - Altera Corporation
Presentation

FC2 - User & Tutorial Session - High Performance Block Design, ICC 2014.09 Update Training, 700M Gate SoC Implementation Lynx Design Flow, High Performance Block Design, ICC 2014.09 Update Training
FC2.3 - Optimized Implementation of a 700M Gate, Gigahertz+ System on a Chip (SoC) Fabricated at 20nm Process Technology Using Synopsys Galaxy Design Platform
Author(s): Takashi Saiki - Fujitsu
PresentationVideo

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