UALink Consortium Recognizes Kishore Mishra's Contribution to the Spec

Most of the work that makes an open standard succeed never shows up in a press release. It happens in spec reviews, working group calls, and the unglamorous business of finding the one ambiguity in a draft that would have cost every implementer six months of silicon debug.

That is the work the UALink Consortium recognized in Kishore Mishra, Sr. Engineering Architect at Synopsys, and a member of the data link layer, transaction layer, and system management working groups at Synopsys. And it is work he shares with a broader team — the PHY, PCIe, and high-speed Ethernet groups whose methods and silicon he drew on to keep pace with a standard moving faster than anything the industry has built before.

Kishore has spent 25 years designing chips, starting at Texas Instruments and Intel and later founding his own start-ups. He wrote the 700-page book Advanced Chip Design. He has worked on PCI Express since Gen 1, more than twenty years ago, and has built controller IP across PCIe, CXL, DDR, AMBA and cache-coherent NoC.

When UALink emerged about a year and a half ago, the fit was immediate.

This is the part our customers feel later. Design teams building accelerator and switch silicon are committing to UALink now, before a broad interoperability track record exists. Every anomaly caught in the draft is an ambiguity that never becomes a respin.

Kishore sits in all three working groups, which gives him something rare — a full-stack view of the specification rather than a single layer.

UALink has come together faster than earlier standards like PCIe, where a generation could take several years. Kishore points to a practical reason Synopsys was able to keep pace: much of the underlying engineering was already familiar. The protocol stack resembles PCIe, the PHY side draws on high-speed Ethernet, and those two Synopsys IP portfolios have together enabled more than 5,000 successful customer tapeouts.

Synopsys UALink IP is built on the same silicon-proven 112G/224G PHY and controller expertise behind thousands of customer tapeouts.

Kishore points to two features as the most consequential for anyone running large accelerator pods: link resiliency and link folding.

For operators of pods scaling toward hundreds of accelerators and beyond, graceful degradation instead of a dropped link is the difference between a serviced node and a stalled job. The Synopsys UALink controller supports both.

Alongside the consortium’s compliance work, Synopsys engages directly with accelerator, switch, and system vendors to validate interoperability ahead of silicon — the same model that made PCIe IP dependable across generations.

Congratulations, Kishore and thank you to the UALink, PHY, PCIe, and Ethernet IP teams whose collective engineering is behind every line of feedback he brought to that committee.

Synopsys is the only IP company on the UALink Consortium Board of Directors, and our UALink IP solution — controller, 112G/224G PHY, UALinkSec security module, and verification IP — is built on interface IP with a silicon record spanning thousands of customer tapeouts.