Synopsys Achieves World's First PCIe 7.0 Subsystem Link at 128 GT/s

AI models keep growing, and so do the systems that train and run them. Every new generation of accelerators, CPUs, memory, and storage moves more data, more often, between more devices. Compute keeps scaling, but system performance depends on how fast data moves between those devices.

PCIe sits at the center of that data movement inside the server. It connects CPUs to accelerators, NICs, SSDs, switches, and retimers. PCIe 7.0 doubles the data rate to 128 GT/s per lane, giving architects the bandwidth to keep pace with AI workloads without adding lanes.

A faster spec is only useful once it works in silicon and in real systems. For PCIe 7.0, Synopsys has been proving that one layer at a time.

Synopsys PCIe 7.0 PHY IP has reached first silicon on multiple advanced process nodes. It has been put through electrical validation under stressed, spec-level conditions and tested for protocol interoperability with leading test equipment partners at 128 GT/s.

At 128 GT/s, copper reach gets shorter, and AI systems are starting to scale past what copper can carry. Optics is moving closer to the PCIe link, which changes how links are designed and validated. Our white paper, Scaling PCIe 7.0 Beyond Copper, describes a measurement-based approach to validating PCIe over optics today while preparing for 256 GT/s.

Proving the PHY is only part of the work. A PCIe 7.0 design also needs the controller, PHY interface logic, and firmware to train a link and keep it stable.

This month, Synopsys engineers demonstrated a PCIe 7.0 RC-to-EP subsystem link operating at the full 128 GT/s data rate. The setup connected a Synopsys PCIe 7.0 Root Complex Subsystem test chip, integrating the controller and PHY, back-to-back with a PCIe 7.0 Endpoint Subsystem prototype on HAPS-200. The Endpoint prototype combined a PHY implemented in silicon with a PCIe 7.0 Endpoint Controller running on the HAPS-200 FPGA Prototyping System, enabling an at-speed, end-to-end PCIe 7.0 subsystem demonstration at 128 GT/s.

The complete link successfully trained to L0, the PCIe state in which normal data transfer occurs, and maintained stable operation across repeated runs at 128 GT/s.

This gives design teams a hardware platform for PCIe 7.0 well before their own SoC returns from the fab. Firmware and software teams can begin bring-up earlier, enabling integration issues to be identified and resolved when they are still faster and less costly to fix.

The team is continuing toward full back-to-back testing with the complete feature set. We'll share more as results come in.

PCIe 7.0 changes more than the data rate. It affects controller architecture, datapath width, and the way SoCs are partitioned. Watch our on-demand webinar, PCIe 7.0? Understanding Why Now Is the Time to Transition, to see what the transition means for your next design.