Scaling PCIe 7.0 Beyond Copper: A System-Level Correlation Approach for PCIe Over Optics

At 128 GT/s, copper is running out of room, and optics is moving into the PCIe link. When it does, traditional electrical test points disappear and simulation alone can no longer predict how the link behaves. This white paper presents a measurement-anchored correlation methodology for PCIe 7.0 over optics, built on a Synopsys PCIe 7.0 PHY and a MACOM EML driver. Read the paper to see the measured results and learn how to validate optical PCIe links today while preparing for 256 GT/s..

What you'll learn:

• Where copper runs out of room at 128 GT/s and when optics enters the PCIe link 
• What changes for validation once the link crosses into the optical domain 
• How to partition a PCIe-over-optics link into domains you can model and correlate 
• What measured results from a Synopsys PCIe 7.0 PHY and MACOM EML driver show 
• How to apply 128 GT/s learnings to 256 GT/s pathfinding