HAPS-80 Prototypes

Deliver Prototypes of ASIC and SoC Designs in Under Two Weeks

Prototypes for ASIC IP and SoC design are the most reliable and affordable way to confirm that new designs are compliant with a particular specification or standard but will also satisfy your customer needs. Synopsys’ HAPS® (High-Performance ASIC Prototyping System) prototyping systems have been designed to deliver maximum system performance and easy integration with physical interfaces, and do so in as short time as possible.

Synopsys HAPS ProtoCompiler software, which has built in knowledge of the HAPS system architecture, automates partitioning and enables an average time to first prototype of less than two weeks and subsequent compile iterations in hours compared to non-integrated prototypes.

HAPS-80 Features:

  • Modular system architecture scales from 26 million to over 1.6 billion ASIC gates to accommodate a range of design sizes, from individual IP blocks to processor sub-systems to complete SoCs. For system capacity ranging from 500K to 4 million ASIC gates, see the HAPS Developer eXpress (HAPS-DX) Series.
  • Provides migration path for single-FPGA IP modules to be integrated into a system of multi-FPGA SoC modules maximizing prototype reuse across engineering teams
  • Enhanced HapsTrak 3 I/O connector technology with high speed time-domain multiplexing delivers up to 3x performance improvement in data throughput over traditional pin multiplexing
  • System definition and bring-up utilities speed hardware assembly and ensure the prototype's electro-mechanical integrity
  • Advanced power and cooling management
  • Design planning tools reduces time-to-prototype by 2-3 months streamlining the transition from block level IP validation to full system integration
  • System configuration software provides access to directly query and control the system configuration of a live system
  • High-speed, nonintrusive, Deep Trace Debug feature enables capture of over 1,000 debug signal bits per FPGA and stores results to on-board memory resources
  • Native Ethernet connection enables global system accessibility via connection to a standard network hub with no additional hardware
  • Multi-design mode to enable execution of multiple designs simultaneously across HAPS systems
  • HAPS UMRBus provide hardware infrastructure, OS device drivers, and various APIs for configuration and data exchange with a Synopsys FPGA-based prototype from Windows or Linux workstation
  • Advanced use modes including hybrid prototyping
  • HAPS-80 prototyping systems are available in any combination of 1, 2, or 4 FPGA model variants



A combination of extensive testing and strict product release criteria helps ensure that HAPS users enjoy the benefits of high availability, reliability, and functional consistency across units.

High Performance

Performance is what has made HAPS prototyping the industry leader for a range of validation scenarios from independent IP blocks to full systems that integrate CPU subsystems.

Scalable Capacity

A modular hardware architecture along with the latest high-capacity FPGA technology allows for HAPS-80 systems to scale from 26 million to over 1.6 billion ASIC gates.

Observability and Controllability

Seamless signal capture across FPGAs and a spectrum of data storage options allow wide access and control with minimal impact to prototyping resources and partition plans.

Easy Bring-Up

IP and ASIC RTL migration technology from the industry's leading EDA vendor reduces your effort to deliver high-performance prototypes.

Connectivity Options

The benefits of stand-alone FPGA-based prototypes are clear, but workstation connectivity for HAPS-80 eases migration from a simulation environment and enable a hybrid system that integrates SystemC/TLM models for the fastest SoC prototype bring-up ever.