TestMAX ATPG

Overview

In this three-day workshop, you will learn how use TestMAX ATPG--Synopsys ATPG Tool--to perform the following tasks:

  • Generate test patterns for stuck-at faults given a scan gate-level design created by TestMAX DFT or other tools
  • Describe the test protocol and test pattern timing using STIL
  • Debug DRC and stuck-at fault coverage problems using the Graphical Schematic Viewer
  • Troubleshoot fault coverage problems
  • Save and validate test patterns
  • Troubleshoot simulation failures
  • Diagnose failures on the ATE

This workshop also includes an overview of the fundamentals of manufacturing test, such as:

  • What is manufacturing test?
  • Why perform manufacturing test?
  • What is a stuck-at fault?
  • What is a scan chain?

This workshop also includes an overview of the DFTMAX and Power-Aware APTG features in TestMAX.
 

Objectives

At the end of this workshop the student should be able to:

  • Incorporate TestMAX ATPG in a design and test methodology that produces desired fault coverage, ATPG vector count and ATPG run-time for a full-scan or almost full-scan design
  • Create a STIL Test Protocol File for a design by using Quick STIL menus or commands, TestMAX DFT, or from scratch
  • Use the Graphical Schematic Viewer to analyze and debug warning messages from Design Rule Check or fault coverage problems after ATPG
  • Describe when and how to use at least three options to increase test coverage and/or decrease the number of required test patterns
  • Save test patterns in a proper format for simulation and transfer to an ATE
  • Validate test patterns in simulation using MAX Testbench
  • Describe the difference between the Transition Delay and Path Delay fault models
  • Use timing exceptions with At-Speed testing to mask slow cells
  • Limit switching activity with Power-Aware ATPG
  • Perform Transition Delay testing including Slack-Based Transition Delay
  • Use On-Chip Clocking (OCC) to provide launch and capture clock pulse for At-Speed testing
  • Generate critical paths from PrimeTime for performing Path Delay testing
  • Use TestMAX Diagnosis features to analyze failures on the ATE
     

Audience Profile

ASIC, SoC or Test Engineers who perform ATPG at the Chip or SoC level.
 

Prerequisites

There are no prerequisites for this workshop. Prior experience with TestMAX DFT, scan insertion, manufacturing test, and writing Synopsys Tcl scripts is useful, but not required.

 

Course Outline 

Day 1

  • Introduction
  • Manufacturing Test and TestMAX ATPG
  • Building ATPG Models
  • Running DRC
  • Fault Models and Managing Faults

Day 2

  • Controlling ATPG
  • Post ATPG Analysis
  • Pattern Validation
  • At-Speed Testing and Constraints

Day 3

  • Transition Delay Testing
  • On-Chip Clocking (OCC) and Compression
  • TestMAX Diagnosis
  • Conclusion
     

Synopsys Tools Used

  • TestMAX ATPG 2019.12 (or TetraMAX 2019.12)
  • TestMAX Diagnosis 2019.12 (or TetraMAX 2019.12)
  • PrimeTime 2019.12
  • VCS 2019.06-SP2
  • Verdi 2019.06-SP2