ProtoSynthesis

FPGA-based prototyping solution

Synopsys ProtoSynthesis, the next-generation FPGA synthesis software solution enables engineers to develop FPGA-based prototypes faster with expanded debug visibility and targeting the highest quality of results (QoR), resulting in faster time-to-market. It is essential that hardware and software development overlap and run in parallel, instead of sequentially. The ProtoSynthesis software reduces time-to-market leveraging a fast runtime combined with the same RTL and compiler as other Synopsys verification tools. The ProtoSynthesis software works with any hardware setup that includes the supported FPGA devices, including Xilinx UltraScale, UltraScale+ and Versal.  

Functionality:

The ProtoSynthesis tool is part of the Synopsys Verification Continuum® platform and incorporates the following functionality:

  • Synthesis software, including rapid bring-up with the shared VCS® simulation compiler, and features that simplify migration from ASIC designs and the import of IP
  • Sophisticated FPGA logic synthesis engine  
  • Built-in instrumentation
  • Xilinx Vivado software, to place and route the design
  • Integration with other Synopsys tools to enhance functionality and provide a seamless FPGA prototyping solution, including DesignWare® IP, VCS simulation, and Verdi® automated debug
ProtoSynthesis Diagram

 

Feature Description
Integration with VCS Unified Compile with direct support for DesignWare IP  Unified Compile functionality allows for the same design to be easily migrated from one Synopsys verification tool to another, from simulation to prototyping. The UC flow uses the same VCS software as a common front-end to parse and elaborate the design and generate a word-level netlist, which can then be read by the synthesis or prototyping tool. This design flow lets you use the same RTL compiler across tools, for consistent RTL resolution between tools. 
UPF support in Unified Compile Flow  Unified Power Format (UPF) is processed by VCS simulator. The power specifications are provided in a UPF file, which can be used by multiple tools. With the unified compile flow, the UPF file is sourced in the VCS command line when the design is first compiled. 
DesignWare IP support  The tool lets you directly integrate or include DesignWare IP, into the FPGA prototype and reduce the risk by using the same IP as the prototype and the ASIC code. 
Verilog force/bind support  Verilog force and bind statements to separate the golden ASIC code from the code for FPGA prototyping. For example, you can use this method to substitute circuitry, change a clock tree, or stub out part of a design that is not needed in the FPGA prototype. 
Integrated RTL debugger  The integrated RTL debugger quickly finds functional errors. You will be able to debug live hardware with the internal design visibility you need while using intuitive debugging techniques. 
Best Quality of Results (QoR)  Best QoR for timing performance and area/cost reduction. 
Automated gated clock conversion  Gated clock conversion (GCC) comprises the functionality used to simplify gated clock and generated clock structures and convert them to FPGA-friendly clock schemes. 
Compiling Incrementally Using the Design Database to SRS flow  Using the -incremental option with run compile command, you can incrementally compile designs from the design database. 
Real number synthesis Real number synthesis is enabled by default and supports synthesis of 32-bit and 64-bit real numbers using DesignWare IP.