What is Silicon Chip Place and Route?

Before the place and route design steps can be performed by EDA software tools, a silicon die design database and the chip’s logical design must be provided to the place and route tool. The design database is like a blank canvas to hold the physical (and logical) design and indicates to the tool the physical size and dimensions of the chip, and the logical design database contains the logic gates and their pin-to-pin connections. 

The challenge for the EDA tool is to place and route the logical design, transforming it into a physical design both correctly and optimally. Given a logical design and empty physical design, there can be many possibilities of place and route solutions; it is not a puzzle with only one solution. They challenge is to arrive at a placed and routed design that meets the designer’s power, performance, and area (PPA) targets as well as physical design rules dictated by the silicon foundry that ultimately manufactures the silicon chip.

Some details regarding the place and route physical design steps:

• Placement:
  • This phase determines where each logic cell (such as gates, flip-flops, or other functional blocks) will physically reside on the silicon chip.
  • The goal is to position these cells efficiently to minimize the distance signals must travel between the cells, which helps reduce power consumption, increase speed, and optimize chip area.
• Routing:
  • After placement, routing connects the cells’ pins by creating physical pathways (wires) called routes, for electrical signals according to the design’s schematic.
  • A silicon chip is built in vertical layers, with lower layers dedicated to the transistor building blocks which make up the logic gates and multiple layers used for routing the wire connections between the gates.
  • The routing tool finds the best paths (or routes) for these connections, ensuring signals reach their destinations without interference, shorting with other routes, and adhering to design rules for spacing, layer usage, and timing.

After the design has been placed and routed by the EDA software, analysis can be performed on the resulting physical design to evaluate its quality. Typical metrics include:

• Total wirelength used to route the design (shorter is usually better)

• Placement and routing congestion (lower congestion is usually better)

• Number of remaining shorts or opens (wiring shorts or opens can occur for some signals if paths cannot be found)

• Number of design rule violations (cases where a design rule violation cannot be avoided)

EDA tools also provide powerful graphical display capabilities showing the logic gate placement and the physical routing paths. Engineers can zoom into desired areas that have issues, congestion, etc. for debug or visualization. 

Figure 1 shows logic gate placement (rectangles):

Synopsys offers comprehensive, automated place and route solutions that create optimal physical designs to meet demanding timing, power, and area requirements, while respecting individual designer constraints and directives. Synopsys products that offer automated place and route functionality include:

• Fusion Compiler
• Custom Compiler
• 3DIC Compiler

These products offer complete silicon design solutions of which place and route is a key part of. As unified environments, they provide feasibility exploration, prototyping, floorplanning, design, optimization, analysis, verification, and advanced packaging, all within the entire silicon chip design journey. Synopsys’ place and route solutions are integrated capabilities in the context of the entire flow, not a discrete, isolated design step. For example, the placement and routing steps are timing and area driven, which tightly connects optimization to the physical design. This provides chip designers with a complete end-to-end integrated solution instead of a set of disconnected software tools.

From early architectural exploration, design implementation, test, IP, software and hardware verification, Synopsys continues to drive the next wave of innovation in silicon chip design.