The Synopsys ARC® xCAM product works with the Synopsys ARChitect Processor Configurator to automatically provide 100% cycle-accurate models that reflect system-on-chip (SoC) designers specific hardware configurations of Synopsys ARC IP. These models allow design verification and provide detailed performance analysis of software before finalizing the hardware design. An underlying generator engine automatically creates the ARC xCAM Cycle Accurate Model by translating the original Verilog RTL into 100% cycle accurate C++ or SystemC models. With the ARC xCAM solution, multiple models are generated to compare alternative approaches against specific code early in the design process, assisting in choosing an optimal configuration.
The ARC xCAM product installs within the ARChitect IP Configurator to generate cycle-accurate models. Once installed, the modeling component can be added to the processor design within ARChitect and options set. The ARChitect solution then builds a 100% cycle-accurate model in minutes.
Upon completion of the ARC IP configuration, the ARChitect solution uses the Synopsys ARC xCAM product to add a step into the build process, generating a cycle-accurate model that reflects the user's configuration automatically.
The ARC xCAM model operates as a target within GDB and the MetaWare Debugger. Using the ARC xCAM solution's 100% cycle-accurate models is as simple as using an ISS or actual hardware.
At any time during the run, access the following profiling information:
- Forward cycle counts
- Backward cycle counts
- Instruction counts
View profiling data:
- Per function - to determine function with the most cycle counts
- Per line of source or disassembly - to find candidates for custom instructions within a function
- Per count - ordered from highest to lowest counts across the entire application
End User Agreement
Downloads and Documentation
- Save tens of man-months of manual SystemC model development work
- Automatically generate 100% cycle-accurate models within minutes of finishing a configuration
- Parallelize hardware and software development
- Quickly iterate through multiple system configurations to determine the best options for your requirements
- Increase the number of develop/debug/optimize cycles to ensure your product meets your requirements
- Prototype earlier in the development cycle to influence prospects and customers
- Provide full core visibility with high resolution to even analyze branch prediction and cache misses
Increase developer productivity
- Integrated with GNU tools and the MetaWare Development Toolkit for optimum profiling and visibility
- SystemC models can connect to wider co-development tool flows to help productivity
|xCAM cycle accurate processor model generator for the ARC 600 family of processor cores||STARs
|xCAM cycle accurate processor model generator for the ARC 700 family of processor cores||STARs
|xCAM cycle accurate processor model generator for the ARC EM family of processor cores||STARs
|xCAM cycle accurate processor model generator for the ARC HS family of processor cores||STARs
|xCAM cycle accurate processor model runtime for ARC processor cores||STARs
|xCAM cycle accurate processor model generator for the ARC EV family of processor cores||STARs