Synopsys' DesignWare® ARC® xCAM product works with the DesignWare ARChitect Processor Configurator to automatically provide 100% cycle-accurate models that reflect system-on-chip (SoC) designers specific hardware configurations of DesignWare ARC IP. These models allow design verification and provide detailed performance analysis of software before finalizing the hardware design. An underlying generator engine automatically creates the ARC xCAM Cycle Accurate Model by translating the original Verilog RTL into 100% cycle accurate C++ or SystemC models. With the ARC xCAM solution, multiple models are generated to compare alternative approaches against specific code early in the design process, assisting in choosing an optimal configuration.
The ARC xCAM product installs within the ARChitect IP Configurator to generate cycle-accurate models. Once installed, the modeling component can be added to the processor design within DesignWare ARChitect and options set. The ARChitect solution then builds a 100% cycle-accurate model in minutes.
Upon completion of the ARC IP configuration, the ARChitect solution uses the DesignWare ARC xCAM product to add a step into the build process, generating a cycle-accurate model that reflects the user's configuration automatically.
The ARC xCAM model operates as a target within GDB and the MetaWare Debugger. Using the ARC xCAM solution's 100% cycle-accurate models is as simple as using an ISS or actual hardware.
At any time during the run, access the following profiling information:
Forward cycle counts
Backward cycle counts
View profiling data:
Per function - to determine function with the most cycle counts
Per line of source or disassembly - to find candidates for custom instructions within a function
Per count - ordered from highest to lowest counts across the entire application