DesignWare IP for 5G Mobile Infrastructure

With the growing volume of data traffic in 5G mobile technologies, the demands on mobile infrastructure is increasing. Growing mobile bandwidth requirements, more connectivity for IoT and advanced autonomous driving technologies and emerging technologies to enable real-time interactive systems require a range of high bandwidth IP solutions to address these needs.

Synopsys offers the industry’s broadest portfolio of interface IP, data converter IP, security IP, and a range of processor solutions to deliver the capacity and performance required by 5G infrastructure applications.

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DDR

  • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
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Ethernet

  • Supports 10/100/1G to 100G, MAC, PCS, and PHY
  • Actively driving TSN and 25G/50G/100G Enterprise solutions.
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High speed SerDes

  • High-quality signal integrity and advanced power management capabilities for PCIe, CCIX, JESD204, Ethernet, CPRI and more
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ARC EV6x Processor

  • Wide SIMD/VLIW processor with ISA optimized for communications algorithms and machine learning
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Security / HSM

  • Hardware Security Modules are standard components for mobile chipsets as the trend for embedded / integrated SIM capabilities are implemented.
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5G NR UE Processing

  • ASIP Tool - Industry leading tool to develop baseband processors. Deploys task-optimized processing solutions with hardware parallelism & custom datapaths while retaining programmability. Ideal to for custom application optimization
  • ARC HSxD - Combined CPU+DSP architecture and multicore control operations; efficient interfacing to hardware accelerators  
  • ARC EV6x - Wide SIMD/VLIW processor with ISA optimized for communications algorithms and machine learning
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PCIe Controller and PHY

  • High-performance, multi-channel PCIe PHY supporting PCIe 4.0, 3.1, 2.1, 1.1
  • Configurable PCIe controller supporting PCIe 4.0, 3.1, 2.1, 1.1
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Analog Front End

  • Delivers GHz channel bandwidth, high QAM, low BOM cost, direct RF conversion with hundreds of implementations
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Analog Front End

  • Delivers GHz channel bandwidth, high QAM, low BOM cost, direct RF conversion with hundreds of implementations
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  • Analog front-end delivers GHz channel bandwidth, high QAM, low BOM cost, direct RF conversion with hundreds of implementations
  • ASIP Designer deploys task-optimized processing solutions with hardware parallelism & custom datapaths while retaining programmability for 5G baseband processing
  • ARC HS4xD offers combined CPU+DSP architecture and multicore control operations, as well as efficient interfacing to hardware accelerators
  • ARC EV6x is a wide SIMD/VLIW processor with ISA optimized for communications algorithms and machine learning
  • Security Protocol Accelerators support regional approved ciphers, hashes, and MAC algorithms to enable flexible solutions for next generation 5G SoCs. True random number generators and other cryptography cores enable designers to build their own solutions. 
  • Supports the latest DDR5/4 standards 
  • Ethernet MAC, PCS, and PHY support 10/100/1G to 100G. Actively driving TSN and 25G/50G/100G Enterprise solutions
  • Multi-Protocol High Speed SerDes PHY delivers high-quality signal integrity and advanced power management capabilities for PCIe, CCIX, JESD204, Ethernet, CPRI and more