Thursday, October 01, 2015
9:00 AM - 10:30 AM |
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| Keynote |
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Silicon to Software - 'Shift Left'
Chi-Foon Chan, President and co-CEO - Synopsys |
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From Silicon to Software, two simultaneous and fundamental trends drive the future. First, a decade of silicon advances brings substantially more computation and a world of Internet of Things (IoT), based on low-power and low-cost silicon capabilities. Second, these advances are leveraged by a massive software push, ranging from embedded software to domain-specific application software.
These trends are leading into a decade of smart everything that will impact both technology and business models. For designers and developers, it will result in increasing pressure to accelerate, or ‘shift left’, schedules regardless of the complexity. Mr. Chan's presentation will look into the innovations and productivity advancements in design, verification, IP and software integrity to help you ‘shift left’ from silicon to software. |
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Thursday, October 01, 2015
10:45 AM - 12:15 PM |
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| A1 - User Session - Testbench Techniques with UVM |
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Verifying C++ Firmware Sequences in UVM Environment
Ashwini Holla - Advanced Micro Devices |
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In AMD designs, a significant number of power management features are being implemented in firmware rather than hardware. Firmware sequences are used to define and control hardware behaviour while stepping through different power states. As a result of such interaction, firmware qualification in VCS is becoming important. This presents a unique verification problem, one of devising a smart approach to verifying C++ firmware sequences in a UVM test environment with RTL design blocks. The standard UVM scoreboard methodology only increased the complexity of verification while not providing the necessary coverage. So a hybrid method of test-based scoreboard combined with transaction collection using the UVM infrastructure was adopted. This paper describes how this method was used to check correctness of firmware programming and sequencing while also ensuring proper functioning of hardware. It has enabled effective qualification of hardware behaviour with firmware early in the design process.
Synopsys Tools Used:
VCS
Target Audience:
Intermediate |
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Replacing Hardcoded Register Values with Hardcore Abstraction
Alex Melikian, Hilmar Van Der Kooij - Verilab Canada |
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Today’s complex protocols typically involve built-in register functionality for configuration and operation purposes. This requires corresponding VIPs to mimic register functionality in order to enable exact behavior and complex operations. VIP developers may resort to using a large number of hardcoded values representing register addresses, reset values, or field locations. However, this approach is prone to errors and demands a high level of maintenance during the course of a project as register definitions often change. Our solution enables VIP developers to include register functionality in a manner that is not only scalable, but also flexible and robust to any changes. The solution involves leveraging the derived UVM register model classes, typically defined for mirroring and automating checks on DUT registers. These derived register classes can be used to create a layer of abstraction, allowing the VIP to be transparent to all pre-defined register related values in the protocol.
Synopsys Tools Used:
VCS
Target Audience:
Intermediate |
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RESSL UVM Sequences to the Mat
Bryan Morris, Jeff McNeal - Verilab Canada |
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Read-Evaluate-Start-Sequence-Loop (RESSL -- pronounced "wrestle") is inspired by the Read-Evaluate-Print-Loop (REPL) found in Lisp and Python. The REPL in these languages encourage a rapid, iterative, and interactive development process allowing the user to easily develop and test new sequences with a minimum of overhead.
In the context of ASIC verification, RESSL enables the iterative development and debug of UVM sequences. Similar to the Lisp REPL, it includes four phases:
Read: A simple interpreter allowing the user to input commands via STDIN. Evaluate: The evaluator takes those commands and executes them. These commands include among others, the ability to clone, alter parameters and start sequences. Start-Sequence: The system starts the sequence (and any sub-sequences) defined. Loop: Clean up and return back to the Read.
This paper provides details on the usage model, implementation, and future work planned for the RESSL.
Synopsys Tools Used:
VCS
Target Audience:
Intermediate |
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| A2 - User & Tutorial Session - PrimeTime PX and Large Scale Design STA |
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Gaining Confidence in Your Publicized Power Numbers
Guy-Armand Kamendjé, Olivier D’Arcy - Huawei Technologies Canada Co., LTD |
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This paper presents our experience with PrimeTime PX SAIF-based power estimation flow. The methodology that we followed allowed us to estimate the power consumption of two designs up to within a few milliwatts when compared to the measured numbers. While presenting the main steps of the methodology, this paper also highlights some intricacies of relying on gate level simulation for early power estimation.
Synopsys Tools Used:
PrimeTime PX, SAIF, PrimeTime
Target Audience:
Intermediate |
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Large Scale Design STA - Hierarchical or Flat, Distributed or Single Machine - Which Way to Go for Timing Signoff?
Vijay Govindarajan, Synopsys |
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Not everyone is working on a 250 million instance design, but there are an increasing number of designs being implemented that are over 100 million instances. At advanced nodes, this could mean signoff with 20 or more signoff timing scenarios. This presents a challenge to design managers and chip timing leads alike as to which approach to take for STA signoff--to signoff flat or take a hierarchical approach? This tutorial will provide an overview of the technologies available within PrimeTime to follow either approach and will outline how designers should make that decision.
Synopsys Tools Used:
PrimeTime SI/ADV
Target Audience:
Design managers with responsibility for STA signoff, chip leads responsible for chip-level timing integration and signoff timing closure |
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| A3 - Panel Session - IC Compiler II |
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Unleashing the Power of IC Compiler II - User Experiences
Rajit Seahra - AMD; Raj Verma - Qualcomm; Thomas Andersen, Costas Conistis - Synopsys |
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IC Compiler II brings break-through technology advancements to tackle the growing challenges in physical design with industry leading performance. In this panel, you will hear from designers about their experiences with this exciting new technology. Design teams will share their use of ICC II to achieve aggressive design objectives and address the system on chip challenges of established and emerging process nodes. Particular focus will be paid to ICC II's new high capacity infrastructure, advanced design planning capabilities, fast, simplified library preparation, and improved optimization convergence including native MV awareness, scalable multi-scenario timing analysis, and advanced clock tree synthesis. If you are interested in cutting edge P&R technology, you need to attend this panel.
Synopsys Tools Used:
IC Compiler II
Target Audience:
Design teams (management & engineers) interested in IC Compiler II |
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Thursday, October 01, 2015
1:15 PM - 3:15 PM |
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| B1 - User Session - Speed Up Your Simulation |
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Architecting Your Way to Acceleration in UVM
Dean Justus, Paul Lungu - Ciena |
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Today's ASICs are increasingly complex, and with the number of gates commonly exceeding 100 million, the simulation as we know it reaches limits in terms of performance. The normal evolution would be to accelerate the DUT at hardware speed. However, the continuous interaction between the verification environment and the DUT implemented in an accelerator impacts the maximum performance one can achieve. The solution would be to synthesize parts of the verification environment responsible for signal toggling into the same accelerator along with the DUT. This has the potential to significantly reduce the overall simulation overhead due to simulator/accelerator interaction. This is an old trick but doing so in UVM is quite new. This paper will discuss in detail the path to architect an UVM environment for acceleration (UVM-A). A seamless methodology to switch from a standard UVM environment to a fully emulation friendly UVM-A environment will be discussed.
Synopsys Tools Used:
VCS
Target Audience:
Intermediate |
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SVAs in IP - The Holy Grail or the Holy Snail
Lawrence Said, Markus Pugi - Cisco Systems |
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Adaptation of System Verilog Assertions (SVAs) has grown considerably due to their ease of use for both simple checks and implementing coverage metrics. As ASICs are pushed to use/reuse external and internal IP blocks of RTL, including their SVAs, DV testbenches consequently inherit these free SVAs. This increasing number of SVAs as a testbench grows can have adverse effects on productivity if not properly managed and implemented. This paper details typical SVA syntax performance issues, why they are difficult to diagnose and identify, and methods to find and address them. All of this gathered from recent experience improving a large-scale environment where more wall clock per simulation was spent in SVAs than in RTL & DV code combined. Further topics include implementing a regex mechanism for starting and stopping assertions, how this compares to typical module based start/stop mechanism and its application to vertical integration.
Synopsys Tools Used:
VCS compiler/simulator, UVM, SVA Library
Target Audience:
Intermediate |
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Method to Partition Your Gate Simulation Debug
Kendall Chan - Advanced Micro Devices |
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Full-chip system on chip (SoC) gate simulations are a challenge for design verification teams. Long compile and run times, large memory host requirements, and difficulty with signal visibility make verifiation debug challenging, though this effort does pay off when you catch the occasional design bug.
A technology from Synopsys called Siloti What-If-Sim-Replay allows you to partition the gate simulation task across the design. The partitions are small in memory footprint and can simulate fast. This paper presents a user experience of how the Siloti What-If-Sim-Replay technology was used in a gate regression flow. The paper describes in detail the simulation harness created to compile and run gate simulations and to check the results.
Synopsys Tools Used:
VCS, Siloti What-if Data Replay (fsdb replay)
Target Audience:
Intermediate |
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| B2 - Tutorial Session - Achieving Optimal QoR with Design Compiler |
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Achieving Optimal Quality of Results Faster with Design Compiler
Tom Wilderotter - Synopsys |
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This tutorial presents best practices and methodologies to use with Design Compiler Graphical to help you achieve optimal quality-of-results while reducing design schedules.
This session will discuss strategies to reduce area and runtime, improve timing, analyze floorplan layouts, and reduce overall power.
The tutorial will also cover the latest enhancements and advances in the Design Compiler family, including usability improvements for multi-bit cell usage, improved congestion analysis, and physical aware clock gating with Design Compiler Graphical.
Attend this session to see how to improve your results and enhance productivity for designs at established and emerging nodes.
Synopsys Tools Used:
DC Ultra, DC Graphical, DC Explorer, Power Compiler
Target Audience:
All existing and new synthesis users |
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| B3 - User & Tutorial Session - IC Compiler & PrimeTime SI |
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Experiences Using PrimeTime Physically-Aware ECO Technology
Khaled Heloue, Rajit Seahra - Advanced Micro Devices |
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In the past few years, Synopsys has introduced many enhancements to PrimeTime's automated ECO Flow, including both logical and physically-aware timing and design rule fixing, and more recently the addition of physically-aware noise fixing technology. During this time, AMD has been an early adopter and a vocal proponent of the ECO flow technology with several tapeouts (and ongoing designs) on 28nm technology nodes and below having actively used at least one aspect of the automated timing and DRC fixing. In this paper, we will give an overview of the fixing effectiveness of PrimeTime's physically-aware ECO flow with respect to setup, hold, transition, and noise fixing, as seen on AMD designs. We will present our general experiences with the technology, including flow implementation, achieved fixing rates of the various checks, runtime and memory usage, and recommendations for getting best results. Our test cases include 16 design blocks on a leading-edge FinFET technology node, with sizes ranging from 250K to 1.5M instances. We will conclude with our overall impression and any enhancements to the tool we would recommend to Synopsys.
Synopsys Tools Used:
PrimeTime, IC Compiler
Target Audience:
Intermediate |
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Script Based DDR Data Bus Balancing Using IC Compiler
Yuri Talaga - Vixs Systems; Jim Lehmann - Synopsys |
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An automated way to balance several data buses to and from four DWC_DDRPHYDATX8 macros and one DWC_DDRPHYAC in a hierarchal block using IC Compiler was developed. The skew requirements for the incoming and outgoing data buses were to be balanced for each DDRPHY and to each other DDRPHY in the block. Making things more of a challenge was the need for a vertical and horizontal version of the hierarchal block. A script based solution was developed that would route the data bits in ICC using routing corridors. Using the longest net length per DDRPHY, the remaining bits net lengths were detoured to match. All nets were buffered as required by DDR constraints using on-route buffering, and the skew delay for each data bus was calculated to verify results. Skew tolerances dictated by the DDR constraints were met using this technique.
Synopsys Tools Used:
IC Compiler and TCL based scripts
Target Audience:
Advanced |
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Using Data Flow Analysis for Floorplanning
Tom Concannon - Synopsys |
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This tutorial presents the three parts of IC Compiler's Data Flow Analysis (DFA) capabilities for floorplanning: Logical Connectivity Analysis, Advanced Flyline Analysis, and Macro Array Editing. With this foundation, we present practical ways to use DFA, including creating initial floorplans for use with DC Explorer using the IC Compiler Design Planning link and optimizing macro placement for best QoR in IC Compiler.
Synopsys Tools Used:
IC Compiler
Target Audience:
Physical Designers |
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Thursday, October 01, 2015
3:30 PM - 5:00 PM |
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| C1 - Tutorial Session - Coverage Closure & Advanced Debug |
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Speed Up Coverage Closure with VC FCA & Echo
Alex Lorgus, Tyler Bennett - Synopsys |
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It is very challenging to achieve 100% of code and functional coverage in a project. One spends a lot of time analyzing the coverage holes and trying to figure out how to create the stimulus to hit those corner cases. This tutorial shows users how to speed up this process by finding unreachable code with VC FCA and analyzing and generating stimulus for functional coverage with Echo, a feature in VCS .
Synopsys Tools Used:
VC FCA, VCS
Target Audience:
Design engineers, design verification (DV) engineers, managers |
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Advanced Protocol Debug with Verdi³ 2015.09
Chris Thompson - Synopsys |
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While many Verification IP products provide error checks for hardware protocols, tracing those errors back to custom design logic requires advanced debug tools. This tutorial illustrates how to use advanced debug features, like Protocol Analyzer and Reverse Interactive Debug, from the Synopsys Verdi3 TM platform to provide what-if analysis of protocol related design errors.
Synopsys Tools Used:
Verdi3, Verdi
Target Audience:
DV engineers, SoC integrators |
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| C2 - User & Tutorial Session - SerDes Integration and RTL Power Estimation |
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Physical and Timing Aspects of Synopsys DesignWare Enterprise 12G SerDes Integration
Boris B. Dzerdz - IDT Canada |
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Over the past decade, Synopsys has established itself as one of the leading SerDes suppliers in the silicon IP market, making analysis of its IP integration experience valuable to ASIC and SoC designers searching for an off-the-shelf serial communication solution.
In this paper, we discuss some of the main technical aspects of Synopsys DesignWare Enterprise 12G SerDes IP integration into IDT's 28nm ASIC. Emphasis is on details of physical and timing integration for reliable system operation.
Synopsys Tools Used:
Tekton, Talus, QCP, PrimeTime-SI
Target Audience:
Intermediate |
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Using SpyGlass to Monitor and Reduce Power in Your Design
Ken Mason - Synopsys |
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This tutorial presents the usage of SpyGlass to reduce the power consumption of ASIC designs. After a general overview of SpyGlass, the session will discuss a technique to measure and reduce the design power at the RTL.
Attend this session to see how SpyGlass Power can help you manage and improve power in your designs. |
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| C3 - Tutorial Session - IC Compiler Update |
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IC Compiler’s Latest 2015.06 Release Delivers Significant Performance Power Area (PPA) Improvements and Faster Closure on Emerging and Established Nodes
Chris Puff - Synopsys |
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IC Compiler is being used for implementing advanced designs at all process technology nodes. In this tutorial, we will focus on the latest 2015.06 release capabilities that help meet aggressive Performance Power and Area (PPA) objectives. For improved performance and smaller area, we will discuss new techniques like pre-route layer promotion, auto NDR (non-default rules), concurrent wire and cell optimization, post-route CCD (concurrent clock and data) optimization, and high resistance optimization and share results. Designers tackling power challenges, especially in FinFET-based designs, will benefit from the new total power optimization algorithms, improvements in low power placement, CTS and multi-bit register banking. This tutorial will also discuss enhancements that support advanced foundry rules and meet manufacturing and DPT requirements at 20/16/14 nm and smaller nodes.
Synopsys Tools Used:
IC Compiler
Target Audience:
Physical designers |
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Analysis of Power Flow in 3-ph Inverters Feeding Inductive Loads in Aerospace Applications
Novica A. Losic - Honeywell Aerospace |
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This work deals with modeling and analysis of power flow in three-phase inverters feeding inductive loads in aerospace applications. Both Sinusoidal PWM (SPWM) and Space Vector PWM (SVPWM) three-phase inverter have been modeled and used to perform the analysis. The notion of the „apparent efficiency" of the inverter, whether SPWM or SVPWM, feeding a load characterized by a Power Factor (PF) other than unity, whereby the efficiency of the inverter is defined traditionally as output Watts divided by input Watts, is introduced and discussed. The inadequacy of the definition for inductive (non-unity PF) loads is explained, accompanied by the simulation results.
Synopsys Tools Used:
Saber 2011.09
Target Audience:
Advanced |
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Analysis in Time and Frequency Domain of PMSM Drive in Aerospace Applications
Novica A. Losic - Honeywell Aerospace |
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This work deals with analysis in both time and frequency domain of a Permanent Magnet Synchronous Motor (PMSM) Drive in Aerospace Applications. A phenomenon of resonance, due to the presence of passive networks in the path of the flow of power towards PMSM, has been observed and discussed and the results of the analysis presented, including determining the resonant frequency and the relevant power, efficiency, and total harmonic distortion figures.
Synopsys Tools Used:
Saber 2011.09
Target Audience:
Advanced |
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Correlation Comparison Between DCT Synthesis and IC Compiler Place and Route Using SPG Flow Versus a Non-SPG flow
Tom Tsopelas, Don Dattani - Cognitive Systems |
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This paper aims to show the benefit of using an SPG flow versus a non-spg flow. It demonstrates that an SPG flow provides better correlation between DCT synthesis and ICC place and route design. The block presented in this paper had a high degree of complexity and congestion due to the nature of the architecture. Using DCT with floorplan information, which included keepouts and bounds, in combination with SPG, was the only means to provide repeatable results with good correlation as well as physical DRC closure.
Synopsys Tools Used:
Design Compiler, IC Compiler
Target Audience:
Introductory |
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