Why Dynamic Power Management Demands Adaptive Clocks

Ask a conventional PLL to change frequency, and it gets back to you within tens of microseconds. And that’s after a relock.^[1],[2] Power events move much faster than the microsecond scale. A voltage droop demands a response in nanoseconds. A DFS shift demands single-digit microseconds. Fixed PLLs, the clock architecture most SoCs use, were built to hold a frequency, but not adapt to dynamic power events. Conversely, adaptive clocks are architected to respond to such events.

On 3nm silicon, V_nom sits near 0.75V^[3] and published V_min figures are around 0.5V.^[4] A worst-case event can cause VDD to reduce by 75 to 115 mV in a few nanoseconds.^[5] These droops are made worse by coinciding first- and second-order droops.^[6] Even at its fastest, the regulator is still microseconds away from reacting and mitigating these excursions.

A droop response must be reflexive. As a di/dt event begins, a droop/glitch detector must detect with enough time for the adaptive clock to respond. Most mitigation systems will only have a few clock cycles^[7],[8] to drop its output to a safety frequency to avoid timing violations. To prevent future timing violations and self-induced droops, the same clock needs to hold and slowly ramp back up to V_nom until the droop fully subsides.

The effectiveness of an adaptive clock is measured in recovered guardband. Without nanosecond mitigation, SoC architects will pad every DVFS operating point for the worst-case droop. Adaptive clocking bought AMD 7–15% in power efficiency;^[10] IBM’s POWER9 cut droop margin in half, worth 8% power or 3.5% performance.^[11]

Not every frequency change is an emergency. Most are scheduled and tied to workload changes. A task manager matches performance to queued workloads. On a shared voltage rail, the performance/power tuning options are split. Teams can scale voltage per block, which requires on-die LDOs and possibly tons of deep-trench decaps, or they can scale frequency. However, this requires a digital adaptive clock. The nuance is subtle, but the digital nature allows teams to distribute the adaptive clock per sub-block while using local power rails.

Power management systems would rarely scale in fine steps because of relock times.^[1],[2] An adaptive clock removes the relock penalty because transitions settle in single clock cycles. Adaptive clocks now make frequency extremely tunable, which software can adjust to match the dynamism of the workload shifts. These fine-grain shifts can drive up to 10% SoC energy savings through distributed clocking.^[9]

The fixed PLL has earned its place. It’s optimized for jitter, lock stability, and spectral purity. It can hold a frequency throughout the lifecycle of a chip. However, by its architecture, fixed PLLs are not power management tools.

The power control loops (droop and DFS) demand a different type of clock. An actuator moves between frequencies in clock cycles rather than lock times. Every upward shift in frequency is followed by a managed, programmable ramp, because a hard frequency jump can cause a di/dt event.

The next power management tool is the SLM Advanced Clock Generator (ACG) IP in the Synopsys Silicon Lifecycle Management (SLM) family. It’s a high-performance fractional PLL with three independent oscillators, delivered as process-portable soft IP so every major clock domain can afford its own instance. Sensors sense and the clock responds.

A regular PLL keeps a frequency; an adaptive clock manages it. For more information, see the Synopsys SLM Advanced Clock Generator IP page: https://www.synopsys.com/solutions/silicon-lifecycle-management/functional-monitors/advanced-clock-generator-ip.html

[1]     Xilinx, “Zynq-7000 SoC: DC and AC switching characteristics,” Datasheet DS191.

[2]     K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, “Temperature-aware microarchitecture: Modeling and implementation,” ACM Trans. Archit. Code Optim., vol. 1, no. 1, pp. 94–125, Mar. 2004.

[3]     D. Schor, “N3E replaces N3; comes in many flavors,” WikiChip Fuse, 2022. [Online]. Available: https://fuse.wikichip.org/news/7048/n3e-replaces-n3-comes-in-many-flavors/

[4]     IEEE Int. Solid-State Circuits Conf., “ISSCC 2025 press kit,” Feb. 2025, papers 29.4 (Synopsys) and 29.5 (TSMC). [Online]. Available: https://www.isscc.org/s/ISSCC2025PressKit.pdf

[5]     D. Kanter, “Adaptive clocking in AMD’s Steamroller,” Real World Technologies, 2014. [Online]. Available: https://www.realworldtech.com/steamroller-clocking/

[6]     Movellus, “Introduction to voltage droop and mitigation techniques,” White Paper Rev. 1.00, Jan. 2025. [Online]. Available: https://www.movellus.com/wp-content/uploads/2025/02/Movellus_Droop_Mitigation_Whitepaper_Rev1.00_1-31-2025_FINAL.pdf

[7]     G. Woods, “Robust dynamic voltage droop mitigation and power management,” Semiconductor Engineering. [Online]. Available: https://semiengineering.com/robust-dynamic-voltage-droop-mitigation-and-power-management/

[8]     Movellus, “Movellus extends droop management leadership with Aeonic Generate AWM3,” Press Release, Apr. 2024. [Online]. Available: https://www.movellus.com/press-release/awm3_release/

[9]     Synopsys, “SLM Advanced Clock Generator IP,” Datasheet, Jan. 2026. [Online]. Available: https://www.synopsys.com/content/dam/synopsys/solutions/slm/datasheets/slm-advanced-clock-generator-ip-ds.pdf

[10] IEEE Int. Solid-State Circuits Conf., “ISSCC 2014 press kit,” Feb. 2014, paper 5.6 (AMD). [Online]. Available: https://www.isscc.org/s/2014-Press-Kit.pdf

[11] IEEE Int. Solid-State Circuits Conf., “ISSCC 2017 press kit,” Feb. 2017, paper 26.5 (IBM POWER9).