Enabling Chip Design Education: Utilizing Synopsys Cloud for the GlobalFoundries and Synopsys ‘Chip Design to Tapeout’ Pilot Program

The semiconductor industry’s need for skilled chip designers continues to grow, and hands-on experience is crucial to bridging the gap between academia and industry. To address this, GlobalFoundries (GF) and Synopsys piloted the ‘Chip Design to Tapeout’ education program, offering students at nearly 40 universities worldwide who volunteered for this pilot the opportunity to take their chip designs from concept to silicon. 

The pilot trailblazed the Synopsys EDA flow for GF’s 180MCU open source industrial manufacturing technology, which now allows all interested researchers regular silicon proof-of-concept for their ambitioned chip design projects. Synopsys Academic & Research Alliances (SARA) is amplifying this effort by championing academic-industry collaboration and creating pathways for the next generation of chip designers to thrive. 

This blog explores how Synopsys Cloud made the ambitious program possible behind the scenes.

The Synopsys Cloud FlexEDA SaaS environment was chosen by the SARA team as a turnkey solution to overcome these barriers. Unlike a “bring your own compute” (BYOC) model which relies on universities’ existing on-premises infrastructure, the SaaS deployment offered everything needed in one package:

• Centralized Compute, Storage, Job Scheduler, and Licenses: All users accessed a secure, virtual desktop environment via their browser, with no local installations or license management required.
• Efficient Onboarding: The onboarding of 200 users from nearly 40 universities was streamlined through batch processing and centralized user management.
• Consistent Experience: Every student used the same EDA tool versions, process design kit, proven design flows and compute resources, eliminating compatibility issues and ensuring a professional, real-world workflow.

The cloud model made it possible for program leads to quickly deploy and update process design kits (PDKs), training materials, and tools in a single location. Students and teams could access new resources instantly, regardless of geography. The collaborative nature of the environment allowed users to learn from each other, share solutions, and support one another, all within the centralized Synopsys Cloud platform.

Design environment support was managed through direct communication between the program leads and Synopsys Cloud Operations, ensuring rapid response to technical questions, onboarding requests, and data management needs.

• Environment Setup: The Synopsys Cloud FlexEDA SaaS environment for this program utilized a 120-core Microsoft Azure® HBV3 virtual machine to run the EDA tools, and the design chamber was equipped with 2TB of Azure NetApp Files (ANF) storage. Each user had credentials to create and manage their own directories within a shared “Projects” folder, ensuring data integrity.
• Full Flow from Concept to GDSII: Both analog/mixed-signal and digital design flows were executed in a virtual Linux desktop environment. Many teams developed analog and mixed-signal designs using Synopsys Custom Compiler™ and PrimeSim™, leveraging the Synopsys analog flow and cloud infrastructure. Similarly, students completed the complete digital design flow using Synopsys Fusion Compiler™, VCS®, Design Compiler®, and PrimeTime®.
• Resource Management: While the allocated compute and storage were sufficient overall, periodic maintenance was needed to clear old processes and optimize job scheduler performance. The project encountered some challenges, such as shared license management and occasional virtual desktop environment memory bottlenecks, which were addressed through agile scaling and the established support model.
• Data Handling: Data transfer in and out of the cloud was tightly controlled. Requests were managed through a central repository, with program leads responsible for distributing design files to students, ensuring both efficiency and security.
• Process Design Kit Improvements: During the pilot, when students encountered challenges with design rules or tool integration, SARA and GF made updates to the GF180MCU PDK to simplify usage, improve documentation, and streamline design workflows. Synopsys would then upload the modified PDK into the central repository in the cloud for all students to access. These prompt improvements and the shared environment made the experience smoother for everyone involved.
• Continuous Learning: The pilot was a valuable learning experience for all involved, including in the areas of technical setup and operational logistics for a dispersed group of this size. The team adapted quickly to reduce impacts from any issues and to ensure a positive educational outcome for the students. The lessons learned from this pilot program will help inform future engagements.

The program’s success was not just in the number of students or universities involved, but in the quality of the experience delivered. Students gained hands-on exposure to the full chip design flow, using the same tools, workflows and foundry as commercial chip designers. The centralized, cloud-based approach allowed educators to focus on enabling learning, rather than supporting a distributed design environment with inconsistent tool versions and infrastructure. 

Interest in replicating the model for future engagements and in other regions is already growing. To support this growing demand, GF offers 3 shuttles per year to tapeout and receive silicon on its regular GlobalShuttle™ MPW program. Access is available via GF’s Value Added Partners. 

As the GF, SARA and Synopsys Cloud teams work together with our industry partners to continue to expand the learning environment, the vision is clear: make advanced chip design education accessible, scalable, and truly industry ready. 

The Synopsys and GlobalFoundries ‘Chip Design to Tapeout’ Pilot Program demonstrates how cloud technology can transform semiconductor education. By removing barriers to tool access and compute resources, plus facilitating collaboration across geographically and organizationally distributed learners, Synopsys Academic & Research Alliances with Synopsys Cloud are partnering with educators to empower the next generation of chip designers by turning theory into practice, and ideas into silicon. 

For academics interested in workforce development and similar initiatives, please contact Synopsys Academic & Research Alliances (SARA).