EDA
System
IP
SolvNetPlus
Training & Education
Overview
University of Illinois Chicago collaborated on a workflow to accelerate design space exploration for GaN tri-gate FinFET devices for advanced power delivery architectures. By combining high-fidelity Sentaurus Device simulations with the PALTO active-learning framework, the team reduced dependence on slow CPU-based simulation, enabled faster GPU-efficient inference, and identified high-performing device candidates with strong current density, suitable threshold voltage, and scalability to multi-fin structures.
Challenges
- Simulation bottleneck: Exploring the design space for multi-fin GaN devices with TCAD was too slow, with runs ranging from minutes to days and convergence not always guaranteed.
- Manual optimization: Traditional trial-and-error workflows required extensive hands-on effort and could demand thousands of simulation runs.
- Performance targets: The team needed a practical way to optimize for high drain current, enhancement-mode operation, compact footprint, and scalability for distributed vertical power delivery applications.
Solution
- Automated framework: The team built PALTO around Sentaurus Device to automate data generation, simulation, and design exploration.
- Surrogate modeling: A lightweight multi-task neural network with a shared backbone and separate heads for maximum current and threshold voltage delivered fast predictions.
- Active learning: Deep-ensemble uncertainty estimates identified which device configurations required high-fidelity validation, reducing unnecessary simulation runs while improving model confidence.
- GPU-efficient screening: Once trained, the surrogate screened large pools of candidate geometries before final Sentaurus Device validation.
Results
- Faster exploration: PALTO delivered 3x faster space exploration with GPU-efficient inference compared with traditional optimization approaches.
- High-throughput prediction: The surrogate predicted outcomes orders of magnitude faster than direct TCAD simulation and supported millions of inferences per minute.
- Strong device candidate: The preferred single-fin design achieved approximately 11 A/mm drain current with a small footprint and suitable threshold voltage for enhancement-mode operation.
- Efficient convergence: The approach converged within roughly 3,000 simulations, representing about 100 days of equivalent direct simulation effort.
- Scalable performance: The optimized design scaled successfully to multi-fin structures and showed strong DC, AC, and thermal characteristics for advanced power delivery use cases.
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