EDA
System
IP
SolvNetPlus
Training & Education
Using Synopsys NanoTime Static Timing Analysis, Intel improved coverage, scalability, and signoff confidence for complex self-timed SRAM timing analysis and Liberty characterization.
Overview
Intel’s advanced memory designs require highly accurate timing verification and characterization across large numbers of SRAM instances, PVT corners, and operating modes. Self-timed SRAMs add another layer of complexity: an external clock triggers internally generated clocks and pulse sequences, while internal events such as decode, wordline activation, sensing, precharge, feedback, and reset logic are governed by self-timed handshaking or completion-detection mechanisms.
Traditional dynamic circuit simulation remains essential for functional validation and detailed analog behavior, but it is vector dependent and difficult to scale to exhaustive timing coverage. To address this, Intel applied Synopsys NanoTime Static Timing Analysis (STA) to achieve fast, vectorless, full-path timing coverage and generate signoff-quality Liberty models for self-timed SRAM designs.
Challenges
- Scaling timing verification across massive SRAM coverage: A typical SRAM compiler can generate 100+ instances, each requiring analysis across 25+ PVT corners. Setup and hold checks can reach approximately 100K, and a single memory-specific wordline-to-bitline check can approach 139K combinations per instance.
- Capturing true worst-case paths beyond simulation assumptions: Conventional SPICE-based analysis often reduces runtime by checking selected near and far wordlines, but actual worst-case paths can occur at different wordlines or decoder combinations that are difficult to predict manually.
- Handling self-timed SRAM complexity: Self-timed memories include internal clock generation, clock shaping, latches, feedback paths, reset logic, and complex timing checks. Accurate arrival modeling at internal clocks and self-timed generator points is required for meaningful analysis.
- Reducing manual setup effort while preserving accuracy: NanoTime can require designer guidance for topology recognition, constraints, exceptions, false paths, multi-input switching, and signal-integrity pessimism. Design changes can trigger updates to timing paths, checks, and constraints.
- Supporting characterization across modes and advanced-node accuracy needs: Self-timed memories often include multiple fuse configurations and DVFS operating modes. Advanced nodes also require tighter correlation between STA and dynamic simulation, including options such as PrimeSim Embedded for improved delay accuracy.
Solution
- Synopsys NanoTime Static Timing Analysis: Intel used NanoTime for vectorless timing verification and Liberty model generation, enabling full path coverage across setup, hold, pulse-width, minimum-period, and memory-specific timing checks.
- LXMEM logic-based memory flow: The LXMEM flow, a NanoTime feature, provided a unified approach for SRAMs and register files, internal simulator-based characterization, automated memory net and topology recognition, automatic bit-column configuration, and improved reporting for memory timing paths.
- Memory-aware automation to simplify setup: LXMEM reduced the need for extensive manual tagging of precharge, write, mux, sense-amplifier, and related memory structures, helping improve consistency and reduce setup risk compared with a traditional manual flow.
- Checkpointing and multi-mode reuse: NanoTime checkpointing allowed Intel to save intermediate analysis states, branch from a validated check-design point, and efficiently generate models for multiple fuse combinations without rerunning the complete flow from the beginning.
- PrimeSim Embedded for accuracy-sensitive analysis: For lower-nanometer designs, Intel evaluated PrimeSim Embedded within NanoTime and observed up to 4% delay accuracy improvement, with expected runtime and memory tradeoffs depending on design size and arc count.
- Downstream .lib correctness for self-timed behavior: NanoTime capabilities such as data-check conversion to external setup/hold checks, minimum-period extraction, and minimum-pulse-width creation helped encode critical self-timed memory behavior for downstream PrimeTime analysis.
Results
Intel’s use of NanoTime improved the practicality and confidence of self-timed SRAM timing analysis and characterization. The approach enabled exhaustive vectorless STA coverage at a scale that is not practical with SPICE-only dynamic simulation, while retaining dynamic simulation for functional and analog validation where appropriate.
- Identified real worst-case timing paths early: NanoTime detected a non-obvious worst-case wordline that would have been missed by checking only nearest and farthest wordlines, enabling timely layout correction early in the design cycle.
- Exposed decoder-dependent setup/hold scenarios: NanoTime identified worst-case vectors through complex decoder combinations that had been missed in margin analysis, improving coverage of critical timing scenarios.
- Enabled scalable signoff-quality coverage: For SRAMs with 100+ compiler instances and 25+ PVT corners, NanoTime provided fast, vectorless timing coverage across large volumes of setup, hold, memory-specific, signal-integrity, and pulse-related checks.
- Improved characterization workflow: LXMEM centralized memory-specific checks, automated key memory-recognition steps, and supported Liberty model generation for self-timed SRAMs across fuse combinations and operating modes.
- Improved advanced-node delay accuracy when needed: PrimeSim Embedded delivered up to 4% delay accuracy improvement in evaluated lower-node designs, giving Intel an option to trade additional runtime and memory for higher accuracy on critical designs.
- Supported closure of multiple Intel SRAM designs: With NanoTime setup, LXMEM assistance, and Synopsys collaboration, Intel was able to analyze and close multiple SRAM designs using a more scalable timing verification and characterization methodology.
Key Technical Evidence
Area | Observation | Impact | Success Story Takeaway |
Coverage Scale | 100+ SRAM compiler instances across 25+ PVT corners | SPICE-only verification is impractical at full coverage | NanoTime enables scalable vectorless coverage |
Memory Checks | 512 wordlines × 136 bitlines × 2 polarities ≈ 139K combinations | Limited vector selection can miss true worst cases | STA finds hidden worst-case paths |
Worst-Case Detection | Worst case found at an unexpected wordline and through decoder combinations | Early layout and margin-analysis fixes | Reduced late-stage timing risk |
Accuracy Option | PrimeSim Embedded showed up to 4% delay accuracy improvement | Higher accuracy with runtime/memory tradeoff | Flexible accuracy-performance optimization |
Flow Automation | LXMEM automates memory recognition and centralizes checks | Less manual topology tagging and more consistent setup | Faster, more repeatable characterization |
For additional technical details, methodology, and design insights presented by Intel at AMS SIG India 2026, access the full conference presentation in the gated proceedings.
Synopsys Solutions Used
Synopsys NanoTime Static Timing Analysis, which includes Synopsys LXMEM logic-based memory flow, Synopsys PrimeSim Embedded Simulator, Liberty Generation for Synopsys PrimeTime full-chip timing analysis
