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Using Synopsys PrimeSim XA and HCVA, MediaTek reduced peak virtual memory by up to 6.91X while maintaining Monte Carlo-level accuracy for robust SRAM yield signoff.
Overview
MediaTek is pushing the boundaries of advanced SoC innovation across flagship mobile platforms and emerging automotive applications. As MediaTek advances high-performance XPU designs—including CPU, GPU, and NPU subsystems—SRAM robustness becomes increasingly critical because SRAM can occupy a large share of overall chip area and must support very different dynamic voltage and frequency scaling (DVFS) requirements across blocks. For leading-edge 2nm designs, this means yield qualification must be effective at both high-voltage, high-frequency operating conditions and ultra-low-voltage operating points optimized for power and leakage.
To make large-instance Monte Carlo analysis practical for 2nm XPU SRAMs, MediaTek deployed Synopsys High-Capacity Variation Analysis (HCVA) with PrimeSim XA. HCVA enabled full-instance-level statistical simulation with substantially lower memory usage and faster turnaround, while preserving accuracy against traditional Monte Carlo for failure signatures and timing distributions.
Challenges
- Meeting robust yield signoff at advanced nodes: At 2nm, design complexity, manufacturing variability, and increased interconnect resistance/capacitance create new yield risks across SRAM peripheral logic and bitcells.
- Addressing both high-voltage and ultra-low-voltage failure modes: High-voltage, high-frequency operation can introduce dynamic IR and pulse-width degradation, while ultra-low-voltage operation increases sensitivity to weak device drive current and local variation.
- Scaling Monte Carlo for large SRAM instances: Traditional brute-force Monte Carlo is theoretically effective but impractical at high sigma targets. A 4.5-sigma peripheral-logic qualification could require up to 1 million Monte Carlo runs without foundry acceleration settings.
- Overcoming compute resource bottlenecks: MediaTek’s large 128KB SRAM instances previously required very large-memory machines—up to the class of 512GB systems typically reserved for block-level runs—and runtimes of approximately three days.
Solution
- Synopsys High-Capacity Variation Analysis: MediaTek deployed HCVA to make large-circuit Monte Carlo practical with minimal impact on timing-measurement accuracy.
- PrimeSim XA simulation infrastructure: HCVA leveraged MediaTek’s existing Synopsys simulator environment, supporting full-instance-level analysis instead of limiting analysis to smaller critical-cut netlists.
- Compatibility with foundry statistical settings: HCVA supported foundry-provided local-factor and Nicell settings, enabling MediaTek to retain established qualification methodology while reducing simulation count and resource requirements.
- Efficient distributed execution and reporting: HCVA bucketed simulation samples into worker directories and produced structured runtime, CPU-time, wall-time, peak-memory, pass/fail, and measurement reports for easier tracking.
- Monte Carlo accuracy for tail-risk discovery: By optimizing variation handling while maintaining statistical spread, HCVA enabled MediaTek to continue targeting tail-end failure mechanisms critical to yield qualification.
Results
MediaTek validated HCVA on both a 128KB single-port SRAM instance and an 8KB double-pump SRAM instance. Accuracy was evaluated during the development phase—when design margins were still strained—using functional vectors that stressed internal design margins. HCVA matched the key failure signatures and timing-distribution behavior observed with traditional Monte Carlo.
- Reduced runtime on the largest SRAM instance: Runtime for the 128KB instance improved from 3 days, 1 hour to 1 day, 20 hours—a 1.55X gain.
- Cut peak virtual memory dramatically: Peak virtual memory for the 128KB instance decreased from greater than 256GB to approximately 37GB, delivering 6.91X lower memory usage.
- Improved capacity on smaller instances as well: For the 8KB instance, runtime improved from 1 day, 6 minutes to 19 hours, 41 minutes, while peak memory dropped from 6705MB to 1408MB, a 4.76X reduction.
- Maintained accuracy for yield qualification: HCVA captured comparable experimental failure results and identical failure mechanisms/waveforms versus traditional Monte Carlo, while timing-arc QQ plots showed aligned 3-sigma spread across multiple timing arcs.
Measured Impact
| SRAM Instance | Metric | Traditional MC | HCVA | Impact |
| 128KB Single-Port | Runtime | 3 days, 1 hour | 1 day, 20 hours | 1.55X gain |
| Peak Virtual Memory | >256GB | ~37GB | 6.91X lower memory usage | |
| Accuracy | 3/300 experimental failures | 2/300 experimental failures | Meeting accuracy | |
| 8KB Double-Pump | Runtime | 1 day, 6 minutes | 19 hours, 41 minutes | 1.22X gain |
| Peak Virtual Memory | 6705MB | 1408MB | 4.76X lower memory usage | |
| Accuracy | 12/100 experimental failures | 9/100 experimental failures | Meeting accuracy |
Synopsys Solutions Used
- Synopsys High-Capacity Variation Analysis (HCVA)
- Synopsys PrimeSim XA
