What is Voltage Drop?

Other sources of voltage drop include inductive reactance and capacitive reactance in alternating current (AC) circuits, as well as switching losses in semiconductors due to the electrical energy required to switch diodes or transistors on or off.

Engineers study and try to reduce voltage drop in everything from power grids to microchips because any loss of voltage reduces circuit efficiency. Additionally, excessive voltage drop can cause components or the circuit itself to malfunction. It is especially critical in both digital and analog integrated circuits (ICs) because voltage drop can cause:

• Functional errors due to low voltage level, registering a binary 1 as a 0
• Excessive heat generation that requires additional power, operating, and capital costs for cooling
• Overheating that leads to component shutdown and eventually mechanical failure
• Consumption of electrical energy in the form of heat generation instead of computing or signal processing

When electrons move through a material, they constantly collide with atoms, other electrons, material impurities, and material defects. When this happens, the electrons lose a small amount of energy as heat. This loss of electrical energy produces a drop in the circuit's electric potential. For most materials, resistance increases with temperature, adding to the voltage drop.

Although this article focuses on voltage drop in electronic circuits for printed circuit boards (PCBs), chip packages, and ICs, it is an issue in electrical power systems for buildings and machines. Electricians follow guidelines in the National Electrical Code and other industry standards to identify and eliminate potential hazards and prevent overheating that can lead to fires. They look at factors such as wire size, bus bar geometry, cable run length, and capacitor placement to manage resistance and inductance.

This loss due to material resistance in electrical conductors is just one source of IR drop. Another is the voltage drop across components in an electrical system. The most obvious components that cause a voltage drop are resistors. But almost every node in a circuit will produce some sort of voltage drop.

The following is a table showing the different types of voltage drop found in both direct current (DC) and alternating current (AC) electrical systems:

The Water Flow Analogy for IR Drop

A good analogy for IR drop in a DC circuit is water flowing through a system with pipes, tanks, valves, connectors, pumps, and turbines:

• Water pressure ~ electric potential (voltage)
• Flow rate (liters per second) ~ electric current
• Obstruction and pipe friction ~ electric resistance
• Pressure drop ~ voltage drop

Just as with copper wire, the longer the pipe or the smaller its diameter, the greater the resistance to flow, causing the pressure to drop as it moves through the pipe. Also, components like valves, couplings, and turbines all pull energy from the flow, reducing the pressure just as electrical components do. Engineers designing electrical circuits and components face the same challenges as hydraulic engineers: balancing the cost and size of a design with performance needs.

Engineers use a variety of methods for voltage drop calculations, depending on its source. In complex electronic systems, engineers use circuit simulators or power modeling tools to capture losses in every conductor and component.

For simple DC circuits, Ohm’s law defines the voltage drop:

Where:

Vd = Voltage drop in Volts

I = Current in Amps

Z = Impedance in Ohms

Impedance is defined as:

$$Z = \sqrt{R^2 + (X_L - X_C)^2}$$

Where:

R = Resistance — ohmic opposition

XL = Inductive Reactance — opposition from inductors

XC = Capacitive Reactance — opposition from capacitors

Although voltage drop comes from many different sources, managing IR drop in packages and ICs is one of the most important areas of modern electrical engineering. Industry trends, such as increased frequency, multi-IC packages, and rising component density, are leading to greater voltage drop in both chip packages and ICs.

With the increasing number and density of data centers, electrical engineers are focusing more on reducing energy consumption in chips and packages. That is why the design flow for both includes power integrity analysis that provides iterative feedback to the electrical system design, leading to an optimized design.

IR drop in semiconductor design can occur in two forms: static and dynamic.

Static IR Drop

Static IR drop is the DC voltage drop across a chip's power delivery network (PDN). It follows Ohm’s law and increases with an increase in the amount of current or the resistance in the circuit. The primary sources of static voltage drop are resistance in the:

• Copper metal layers in the chip or the interconnects
• Copper vias vertically connecting the metal layers
• Package leads and solder in the ball-grid-array (BGA) connections
• Loose connections in the mechanical connectors on the package PCB
• Traces on the package PCB

Engineers try to minimize static IR drop because if the voltage supplied to a region of the chip drops too low relative to the supply voltage, transistors in that region will switch slower than their expected frequency. This can reduce the chip's effective clock speed or lead to a logical malfunction.

Dynamic IR Drop

When a large number of transistors on a chip switch on or off simultaneously, they can cause a rapid increase in the local flow of current. And since IR drop is current multiplied by resistance, the voltage drop spikes upward. In addition to the increase in current, the change in current generates a magnetic field that generates inductance in the circuit, resulting in an even larger spike in voltage drop.

For a dynamic IR drop, the following equation defines the voltage drop:

$$V_{drop} = (I \times R) + \left(L \times \frac{dI}{dt}\right)$$

Where:

Vdrop = IR Drop

I = Current

R = Resistance

L = Inductance

$$\frac{dI}{dt} \text{ = change in current over time} $$

A variety of sources generate this type of voltage drop, including:

• Inductance in the package bond wires, solder bumps, and PCB traces
• Interconnect inductance
• Inductance between power and ground planes

The change in current and inductance causes an effect on the part of the PDN connected to the power source, the power rail, and the side portion connected to ground — the ground rail. The transient spike in current causes the power rail to drop in voltage, called voltage droop, while the ground rail experiences a temporary increase in voltage, called ground bounce. This causes transistors to see less voltage than expected at the supply and a higher voltage at ground, reducing the voltage difference between the supply and ground and, in turn, slowing switching speed.

Engineers deploy a variety of approaches to minimize voltage drop in electronic circuits, such as PCBs, multichip packages, and ICs. Most approaches focus on reducing resistance, minimizing inductance, or avoiding current spikes in dynamic IR drop. Some of the most common solutions are:

• For PCBs:
  • Replace power traces with power planes or fill unused areas with copper for power transmission
  • Widen or thicken traces
  • Shorten the current path whenever possible by placing power-hungry components as close to power sources as possible
  • Increase the number of vias between layers
  • Add decoupling capacitors close to power pins to mitigate dynamic IR drop
  • Deploy thermal management to keep temperatures within acceptable ranges
  • Provide a low impedance return path to reduce ground bounce
  • Lay out trace, wire, power plane, and ground plane placement to minimize inductance
• For multichip packages:
  • Manage inductance between chips and interconnects
  • Include through-silicon vias (TSVs) to move power from the bottom of the package to chips at the top while also managing inductance
  • Use interposers to move power between chips
  • Increase the number of microbumps connecting chips to interposers
  • Deploy decoupling capacitors where needed
  • Lay out conduction, ground, and power paths to minimize induction
• For ICs
  • Use wider power grids and thicker power layers
  • Deliver power to functional blocks with power rings
  • Include on-die decoupling capacitors
  • Use power gating, completely cutting power to idle blocks in the chip
  • Leverage clock gating to avoid sending flip-flop signals through idle data paths
  • Employ design rules to minimize induction

Today, engineers have a variety of capable simulation tools to help them identify voltage drop issues and implement solutions. When choosing a solution, engineers need to ensure that their power simulation software works with their EDA tools to minimize the effort required to use the circuit layout.

For most digital IC designs, engineers start managing voltage drop when they first lay out the circuit's behavior using the register-transfer-level (RTL) design process during the optimization of performance, power, and area (PPA) phase. Engineers can use the proposed circuit with Synopsys PrimePower to analyze, profile, and reduce power at the RTL level.

During silicon chip prototyping, implementation, and optimization, using EDA tools, such as Fusion Compiler and 3DIC Compiler (for multi-die designs), along with in-design multiphysics fusion capabilities, allows designers to predict, find, and correct potential voltage drop issues before the design is finalized.

Understanding voltage drop in PCBs starts with a power integrity tool like Ansys SIwave PCB and package electromagnetics simulation software. It has the advantage of not only calculating static and dynamic IR drop but heat generation for thermal management simulation, along with signal integrity and EMI.

For ICs and multichip packages, engineers use a digital power integrity sign-off simulation package, such as Synopsys RedHawk-SC software, to combine simulations of the PCB, package substrate, chip, and chiplet PDNs. Similarly, engineers use a tool like the Synopsys Totem power integrity sign-off platform for analog or mixed-signal ICs.

The big challenge in power integrity simulation for ICs is the large number of possible signal combinations, far too many to analyze explicitly. Because of this, engineers use one of three approaches to exercise the IC's circuits and calculate the voltage drop:

• Vector-Based Analysis

Engineers use the proposed switching activity from gate-level or RTL simulation to generate a set of vectors that specify the logical state (0 or 1) of every electrical connection (node) in the design. The advantage of this approach is that it tests the chip's real-world states. The disadvantage is that users may miss worst-case voltage drop states.

• Vectorless Analysis

Early in the design process, engineers use a statistical estimate of power levels to construct a worst-case current profile. The advantage is that it is fast and doesn’t require running multiple states as in a vector-based analysis. The disadvantage is that it can overestimate the voltage drop.

• Dynamic Analysis

When engineers need a more accurate picture of voltage drop in their ICs, they use a full-time domain transient simulation of the PDN with a tool like SigmaDVD in Synopsys RedHawk-SC software. It uses the same data as a vector-based analysis but solves for the resistance, inductance, and capacitance (RLC) values of the circuit PDN at every timestep. This is the best approach for determining dynamic IR drop and ground bounce. It also allows for modeling of voltage drop control solutions like power gating and other highly transient events in the IC. The disadvantage is that it can take more time to calculate.