SNUG France 2016 Proceedings

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Complete Proceedings


User Papers and Presentations
A1 - Advanced Design Methodology
In-design Track Fill in IC Compiler II (Technical Committee Award Honorable Mention)
Author(s): Didier Gueze - STMicroelectronics
PaperPresentation

Merging ST Low Uncertainty Clock Tree with ICC2 Multi-Source Clock Tree Methodology for Better QoR
Author(s): Pierpaolo De Laurentiis, Alberto Ferrara - STMicroelectronics; Francesco Lannutti, Aurelio Monti - Synopsys
PaperPresentation

RM Flow Customization Experience
Author(s): Giacomo Cappellin - STMicroelectronics
PaperPresentation

A2 - Adopting UVM Methodology
Yet Another Memory Manager (YAMM)
Author(s): Ionut Tolea, Andrei Vintila - AMIQ Consulting SRL
PaperPresentation

A3 - Power Estimation and Analysis
Using Siloti for Early and Accurate Power Estimation
Author(s): Cyril Chevalier, Audrey Le-Clercq - STMicroelectronics
PaperPresentation

A4 - Design for Test and Compression
DFTMAX-Ultra to Enable High Test Coverage for an Ultra-Low Pin Count Design Embedding a Test Mode Controller
Author(s): Mohrad Mammasse - STMicroelectronics
PaperPresentation

Run Time Reductions for Fast DFT Development
Author(s): Fabien Chiantia, Cedric Escallier - STMicroelectronics
PaperPresentation

Using DFTMAX Shared IO on a Complex ASIC, a User Experience
Author(s): Benoit Leconte - Atos/Bull
PaperPresentation

A6 - AMS Simulation and Debug
A GVI SystemVerilog Nettype Ready for Mixed-signal Simulations
Author(s): Sebastien Cliquennois, Francois Ravatin - STMicroelectronics
PaperPresentation

PageFlash Memory Verification: Co-simulation Methodology for Early Debug and Extensive Coverage Based on VCS AMS (CustomSim-VCS)
Author(s): Enrico Castaldo - STMicroelectronics
Presentation

B1 - Congestion and Area
Improve Predictability and Routability by Anticipating CTS Routing Topology
Author(s): Luc Sponga, Corine Pulvermuller - STMicroelectronics; Sébastien Paquet - Synopsys
PaperPresentation

Reduce Chip Area in a High Routing Congested ARM CortexM3 Design
Author(s): Jens Mayer - Micronas New Technologies
PaperPresentation

Use of Physical Feedthroughs in a Mixed Signal Design with IC Compiler and IC Compiler II
Author(s): Christelle Leherpeur - STMicroelectronics
PaperPresentation

B2 - RTL Checks and Restructuring
Conclusive Formal Verification of Clock Domain Crossings using SpyGlass-CDC (Technical Committee Award)
Author(s): Mejid Kebaili, Jean-Christophe Brignone - STMicroelectronics; Guillaume Plassan, Jean-Philippe Binois - Synopsys
PaperPresentation

RTL Restructuring with Massive Feedthrough to Allow Channel-less Implementation
Author(s): Yann Bonhomme - STMicroelectronics
PaperPresentation

SpyGlass Based DFT Checks
Author(s): Philippe Debaud - STMicroelectronics
PaperPresentation

B3 - Sign-off
Improved Turnaround Time and Performance using Parametric OCV in 28nm FD-SOI Technology (1st Place - Best Paper)
Author(s): Tarun Chawla - STMicroelectronics
PaperPresentation

Noise/Power Sign-off ECO Methodology and New Advanced Features
Author(s): Olivier Corvoisier - Atos/Bull; Patrick Belmond - Synopsys
PaperPresentation

B4 - Physical Aware Design for Test and Safety for ISO 26262
Alternative DFT Solutions to Cope with Physical Congestion
Author(s): Matthieu Sautier, Mohamedarif Alarakhia, Rachid Idrissi - STMicroelectronics
PaperPresentation

Using DFTMAX with both Asynchronous and Synchronous On Chip Clock Controllers (OCC), in a Highly Constrained Environment, a User Experience
Author(s): Maxime Peycelon - Thales; Philippe Rossant - Synopsys
PaperPresentation

B5 - SoC Prototyping
3D Stacked Sensor Prototyping using HAPS-70: Maximizing HAPS Utilization by using a Multi Design Approach
Author(s): Hubert Deborgies - STMicroelectronics
PaperPresentation

B6 - Advanced Analog Verification Flows
Innovative Propagation Methodology for Diodes and Clamps by Using TCL-CCK Advanced Capabilities in Synopsys Circuit Check
Author(s): Luca Togni, Mauro Fragnoli, Paolo Ghigini, Salvatore Santapa, Pierluigi Daglio, Alessandro Valerio - STMicroelectronics; Carlo Borromeo - Synopsys
PaperPresentation

Insights about Ageing Simulation with Fast SPICE CustomSim (XA) Memory Applications at STMicroelectronics
Author(s): Florian Cacho, Atul Bhargava, Radhika Gupta, Dorfy Rao - STMicroelectronics
PaperPresentation

System Level Verification with CustomSim PCM (Phase Change Memory) Built-in Cell (2nd Place - Best Paper)
Author(s): Chantal Auricchio, Alberto Balzarotti, Massimo Borghi, Alessandro Valerio - STMicroelectronics; Tien Pham, Claudio Rallo - Synopsys
PaperPresentation

C1 - Design Planning with IC Compiler II
28nm FD-SOI FlipChip Design with IC Compiler II
Author(s): Raphael Theveniau - STMicroelectronics; Alain Boyer - Synopsys
PaperPresentation

C2 - Verification for Safety
A New Methodology for Automotive Design Robustness to Defects, Using Certitude at RTL and Gate Netlist Level
Author(s): Hubert Marcel, Aymeric Leroy - STMicroelectronics
PaperPresentation

C3 - Advanced Equivalence Checking Flows
Optimizing Finite State Machine Functional ECOs with Formality Ultra
Author(s): Andrea Di Ruzza - STMicroelectronics
PaperPresentation

C4 - SoC Test ATPG, Diagnostic and Repair for Yield
Fast Yield Ramp by Correlating Failed Test Diagnostics and Fab-related Design Hotspots (3rd Place - Best Paper)
Author(s): Nelly Feldman - STMicroelectronics; Christophe Suzor, Salvatore Talluto - Synopsys
PaperPresentation

Path Delay HOLD Checking and Diagnosis
Author(s): Nicolas Falcot, Cédric Escallier - STMicroelectronics
PaperPresentation

C5 - IP & Complex Subsystem Prototyping
FPGA Prototyping of a Complete System-on-Chip with the HAPS-DX7
Author(s): Sandro-Diego Wölfle - Hyperstone GmbH
PaperPresentation

Publication Only
AMS MASIS Wrapper Usage for Efficient Test Control
Author(s): Livier Lizarraga, Cédric Escallier - STMicroelectronics
Publish Only

Pessimism Reduction During STA On a High Performance STM32 Microcontroller
Author(s): Nathalie Meloux - STMicroelectronics
Publish Only

Tutorials
A2 - Adopting UVM Methodology
Key Techniques to Speed Up Debug and Verification Closure - Recent Innovations in Verdi
Author(s): Xavier Mathes - Synopsys
Tutorial

A3 - Power Estimation and Analysis
Setup, Analysis and Debug of Multi-Voltage Design in PrimeTime PX
Author(s): Thomas Ryan - Synopsys
Tutorial

A5 - FPGA Implementation
Accelerate Your FPGA Design Schedules with Synplify Premier
Author(s): Laurent Sol - Synopsys
Tutorial

A6 - AMS Simulation and Debug
Debug an ADC Design with UPF Support in Verdi
Author(s): Pierre-Yves Alla - Synopsys
Tutorial

B3 - Sign-off
Next Generation Low Power ECO for Signoff
Author(s): Nathalie Zaghlan - Synopsys
Tutorial

B4 - Physical Aware Design for Test and Safety for ISO 26262
Lowering DPPM and Testing Safety-Critical Circuits with Synopsys Test Automation Tools
Author(s): Philippe Rossant - Synopsys
Tutorial

B5 - SoC Prototyping
How Flexible Debug Can Speed Physical Prototype Bring-Up and Software Development
Author(s): Achim Nohl - Synopsys
Tutorial

C1 - Design Planning with IC Compiler II
Floorplanning Large Blocks Using IC Compiler II
Author(s): Gaspard Thaller - Synopsys
Tutorial

C2 - Verification for Safety
Designing Safer Cars - A Journey in ISO 26262 Territories
Author(s): Jean-Marc Forey - Synopsys
Tutorial

C3 - Advanced Equivalence Checking Flows
Formality Complete Low Power Verification and Formality 2016.03 Update
Author(s): Robert Hatt - Synopsys
Tutorial

C4 - SoC Test ATPG, Diagnostic and Repair for Yield
Solving Application Specific SoC Test, Diagnostics, and Repair Challenges
Author(s): Yervant Zorian - Synopsys
Tutorial

C5 - IP & Complex Subsystem Prototyping
Adapt, Port, and Integrate Quickly - Prototyping the Right Way
Author(s): Philippe Borges - Synopsys
Tutorial

C6 - Synopsys Custom and AMS Solution
AMS Simulation Update
Author(s): Ravi Tembhekar - Synopsys
Tutorial

Custom Compiler - Assisted Layout Automation Walk-Through Demo
Author(s): Guillaume Thomas - Synopsys
Tutorial

Under the Hood: Custom Compiler Design Environment
Author(s): Guillaume Thomas - Synopsys
Tutorial
SNUG Silicon Valley Keynote

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