SNUG France 2015 Proceedings

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Complete Proceedings


User Papers and Presentations
A1 - Clock Domain Crossing Checking
SDSAC - Self-Driven Synchro Analyser and CDChecker. A GCA Based Method for CDC and Synchronizers Analyser
Author(s): Fabio Crippa, Antonio Griseta - STMicroelectronics
PaperPresentation

A2 - Testbench Qualification and Formal Verification
Formal Qualification of Functional and Connectivity Formal Verification Environments at SoC Level Using Synopsys Certitude
Author(s): Massimo Zendri - STMicroelectronics
PaperPresentation

A3 - IC Compiler II
ICC/ICC II Physical Implementation Comparison of a GPU Partition (1st Place - Best Paper)
Author(s): Anna Asquini, Corine Pulvermuller - STMicroelectronics; Vincent Sornette - Synopsys
PaperPresentation

A4 - Design for Test and ATPG
MAXtestbench - A Technology to Manage STIL Pattern Qualification in Complex SoC Verification Environment
Author(s): Guillaume Costrel de Corainville, Mickael Broutin - STMicroelectronics
PaperPresentation

TetraMax Power Aware ATPG Capabilities on a Production Chip, a User Experience (Technical Committee Award Honorable Mention)
Author(s): Julien Pouget, Joseph Alan, Guillaume Megrette - Ericsson; Philippe Rossant - Synopsys
PaperPresentation

A5 - Custom Design
FDSOI - An Interoperable Technology
Author(s): Gilles Namur - STMicroelectronics
Presentation

A6 - AMS Verification
Automated Flow for High DC Current Verification
Author(s): David Turgis, Faress Tissafi Drissi - STMicroelectronics
PaperPresentation

Extending New Verification Techniques to Mixed-Signal SoCs with VCS AMS
Author(s): Pierluigi Daglio, Mauro Scandiuzzo, Alessandro Valerio - STMicroelectronics; Helene Thibieroz, Massimo Prando, Carlo Borromeo - Synopsys
PaperPresentation

Simulation & Silicon Verification of Adaptive Voltage Scaling for Real Applications
Author(s): Darayus Adil Patel, Robin Wilson, Franck Gardic, Sylvie Naudet - STMicroelectronics; Arnaud Virazel, Patrick Girard - LIRMM; Philippe Brahic - Synopsys
PaperPresentation

B1 - Advanced Low Power Synthesis Techniques for Energy Management
Advanced Synthesis Technique Using Target Library Subset (Technical Committee Award)
Author(s): Laurent Besson - STMicroelectronics
PaperPresentation

Minimum Energy Design for Sub-threshold Wireless Sensor Nodes
Author(s): Seng Oon Toh, James Myers - ARM
PaperPresentation

Succeeding in Implementing a Low-Power SoC with Power Islands
Author(s): Lucille Engels, Bruno Bailly, Andréa Bonzo, Frédéric Bunoz, Guillaume Cogniard, Faustine Coguen, Sébastien Gaubert, Grégoire Gimenez, Rémi Malaquin, Hai Yu - Dolphin Integration
PaperPresentation

B2 - Adopting UVM Methodology I
A Comprehensive UVM Verification Environment for MPEG Transport-Stream Processing
Author(s): Filippo Borlenghi, Simone Borri, Gherardo Gorni - ALi Europe
PaperPresentation

Adopting UVM Methodology for IP Level Verification
Author(s): Giovanni Auditore, Francesco Rua' - STMicroelectronics
PaperPresentation

B3 - Physical Implementation and Design Closure
A53 Core Optimization to Achieve Performances
Author(s): Calogero Timineri, Julien Buvat, Julien Guillemain, Sébastien Peurichard - STMicroelectronics
PaperPresentation

In-Design Metal Fill Insertion for Faster Timing Convergence (2nd Place - Best Paper)
Author(s): Raphael Gras, Ahmed Oumina - STMicroelectronics; Emmanuel Pluchart - Synopsys
PaperPresentation

B4 - Improving Test Quality and Yield
High-end Test Compression Methodology for Low Pin Count Products in Secured Environment
Author(s): Caroline Carin, Arnaud Donné - STMicroelectronics
PaperPresentation

Using TetraMAX Diagnosis for Silicon Debug and Pattern Masking Delivery, on a Complex 28nm FDSOI SoC, Embedding DFTMAX with Serializer Compression Technology
Author(s): Rachid Idrissi, Mohamedarif Alarakhia - STMicroelectronics; Philippe Rossant - Synopsys
PaperPresentation

B6 - Parasitic Extraction and Reliability Analysis
Automatic Feed-through Parasitic Extraction for Memory Compiler Spice Simulations
Author(s): Fabien Leroy - ARM
PaperPresentation

EM/IR Verification of a 14FDSOI Video DAC Using CustomSim-RA
Author(s): Alejandro Chimeno, Francois Lemery, Véronique Bessodes, Nicolas Pelloux - STMicroelectronics
PaperPresentation

Reliability Checks on Signal and Supply Net Topologies of Mixed Analog and Digital and Power ICs
Author(s): Marco Raimondi, Francesco Adduci, Paolo Valente - STMicroelectronics; Claudio Rallo - Synopsys
PaperPresentation

C1 - Advanced Physical Synthesis and Design Exploration
Standard Cells Placement Exchange Between Design Compiler Graphical and IC Compiler (3rd Place - Best Paper)
Author(s): Jean-Marc Calvez, Sébastien Peurichard, Choukri Saidi - STMicroelectronics
PaperPresentation

C2 - Adopting UVM Methodology II
Migrating to UVM Verification Environment for Imaging Applications
Author(s): Kevin Rowley, Boris Rizov - Apical Imaging
PaperPresentation

C3 - Characterization and Sign-off
CCS Noise Library Generation and Checking
Author(s): Benoît Lasbouygues - Atmel Corporation
PaperPresentation

Tutorials
A1 - Clock Domain Crossing Checking
New Static Technologies - Clock Domain Crossing
Author(s): Alberto Baldi - Synopsys
Tutorial

A2 - Testbench Qualification and Formal Verification
New Static Technologies - VC Formal Platform
Author(s): Patrick Blestel - Synopsys
Tutorial

A3 - IC Compiler II
IC Compiler II - Accelerating Products to Market with the Power of 10X
Author(s): Neeraj Kaul, Sanjay Bali - Synopsys

A4 - Design for Test and ATPG
Meet Your Test Quality and Cost Goals on Schedule
Author(s): Alfredo Conte - Synopsys
Tutorial

A5 - Custom Design
Handling Electromigration for Custom Design with FinFET Devices Using Custom Designer
Author(s): Guillaume Thomas - Synopsys
Tutorial

B2 - Adopting UVM Methodology I
Utilizing VIP Test Suites
Author(s): Xavier Mathes - Synopsys
Tutorial

B3 - Physical Implementation and Design Closure
Fast ECO Extraction and Other Techniques for Optimizing Timing Closure TAT
Author(s): Emmanuel Pluchart - Synopsys
Tutorial

B4 - Improving Test Quality and Yield
Yield Investigations with Critical Design Patterns
Author(s): Christophe Suzor - Synopsys
Tutorial

B5 - SoC Prototyping I
Successful Complex GPU IP Implementation on Synopsys HAPS Platforms Using ProtoCompiler
Author(s): Andy Jolley - Synopsys
Tutorial

C1 - Advanced Physical Synthesis and Design Exploration
Achieving Optimal Quality of Results Faster with Design Compiler
Author(s): Jean-Pierre Popieul - Synopsys
Tutorial

C2 - Adopting UVM Methodology II
Verdi Debug Platform (Planning, Coverage, HW/SW)
Author(s): Xavier Mathes - Synopsys
Tutorial

C3 - Characterization and Sign-off
Latest Advancements for Handling Local Variation Effects in Timing Analysis
Author(s): Nathalie Zaghlan - Synopsys
Tutorial

C5 - SoC Prototyping II
Best Practices for Implementing ASIC designs to FPGAs and Boosting Timing Performance (Tips and Techniques from the Field)
Author(s): Paul Owens - Synopsys
Tutorial

How to Achieve a Working FPGA Prototype Faster by Using a Transactor-based Prototyping Flow
Author(s): Laurent Sol - Synopsys
Tutorial

C6 - Advanced AMS Verification
Harnessing the Power of AMS-testbench for Verifying a Mixed-signal SoC environment
Author(s): Pierre-Yves Alla - Synopsys
Tutorial

Mixed-Signal Verification of UPF Based Designs - A Practical Example
Author(s): Andy Milne - Synopsys
Tutorial

Combo
C4 - SMS & SHS Technologies for IEEE 1500 SoC
SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System
Author(s): Steven Oostdijk - Synopsys; Luca Ganatea - STMicroelectronics
Tutorial
SNUG Silicon Valley Keynote

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