Thursday, September 24, 2015
9:15 AM - 10:30 AM |
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| Keynote |
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Silicon to Software: Shift Left
Deirdre Hanford, Executive Vice President, Customer Engagement - Synopsys |
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From Silicon to Software, two simultaneous and fundamental trends drive the future. First, a decade of silicon advances brings substantially more computation and a world of Internet of Things (IoT), based on low-power and low-cost silicon capabilities. Second, these advances are leveraged by a massive software push, ranging from embedded software to domain-specific application software.
These trends are leading into a decade of smart everything that will impact both technology and business models. For designers and developers, it will result in increasing pressure to accelerate, or ‘shift left', schedules regardless of the complexity. Ms. Hanford's presentation will look into the innovations and productivity advancements in design, verification, IP and software integrity to help you ‘shift left' from silicon to software. |
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Thursday, September 24, 2015
10:45 AM - 12:15 PM |
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| A1 User Session - Deploying Formal Verification |
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From Specification to Complete RTL Verification Using Formal Methodology
Suckheui Chung - AMD |
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Formal verification is challenging and results vary due to many factors. However, there are many applications where the results justify the investment. This paper presents one such approach that led to extensive formal validation on a block thereby achieving 100% functional coverage, a goal that is nearly impossible to reach through traditional functional simulation, random or directed. Our approach involved writing a synthesizable RTL model using System Verilog Assertions on a design that is highly complex but has well defined end to end points. I will show in detail how to simplify this daunting complexity and valid using formal techniques. This paper discusses trade-offs, mapping from specification to assertion properties and debug to meet your coverage goal. This approach found a bug which could not be found easily using traditional functional simulations.
Synopsys Tools Used:
VC-Static
Target Audience:
Expert |
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Formal Verification of a Multistage Arbiter
Shahid Ikram, Craig Barner, John Sweeney, and Jim Ellis - Cavium; Bill Dufresne - Synopsys |
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We are presenting our work on formal verification of a multi-stage arbiter using the new Synopsys formal tool (VC-Formal). The arbiter implements a priority-based arbitration scheme at the first-level and a round-robin scheme at the second-level. The main concern was to show that the arbiter is starvation free. A testbench was available but could not guarantee absence of starvation. However the testbench was helpful to create a formal verification (FV) environment around the arbiter's RTL. The FV environment tracks the requests, grants as well as outstanding credits. Initial debugging was done using auto-generated properties (AEP). Later on, a rich set of properties for verification and coverage were written and proven. We found a starvation case in the design and proved that the fixed design is bug-free. Complete Functional coverage of the design was validated using formal assertion coverage. VC-Formal uses Verdi as debugging tool that was extremely useful.
Synopsys Tools Used:
VCFormal, Verdi, VCS, AEP, FV assertion coverage
Target Audience:
Intermediate |
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| B1 Tutorial Session - Synthesis |
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What's New with Synthesis from R&D's Perspective
Janet Olson - Synopsys |
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Advances in process node, design complexity, and the need for faster performance and/or smaller designs have driven the need for new technologies in Design Compiler. Recent releases of Design Compiler provide new functionality for area improvement, small geometries, congestion optimization and other improvements for QoR and runtime. Come learn about these new Design Compiler capabilities from R&D's perspective.
Synopsys Tools Used:
Design Compiler, Design Compiler Graphical, DC Explorer
Target Audience:
All synthesis users |
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Achieving Optimal Quality of Results Faster with Design Compiler
Tom Wilderotter - Synopsys |
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This tutorial presents best practices and methodologies to use with Design Compiler Graphical to help you achieve optimal quality-of-results while reducing design schedules.
This session will discuss strategies to reduce area and runtime, improve timing, and improve congestion. This will include the latest implementation features in DC Graphical. The emphasis will be on best practices to debug your designs, and techniques to improve optimization within your user scripts and methodology.
Attend this session to see how to improve your results and enhance productivity for designs at established and emerging nodes. |
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| C1 Tutorial & User Session - ICC and Design Planning |
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ICC 2015.06 Update - Highlighting the Latest Capabilities
Dave Power - Synopsys |
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Learn about the new features and enhancements available in the K-2015.06 release of IC Compiler. Topics presented will range from advanced technology updates, projects to help improve QOR, and improvements to aid with faster design closure.
Synopsys Tools Used:
IC Compiler
Target Audience:
Physical design engineers and current users of IC Compiler |
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DFA One Step Further - Quicker Floorplan Convergence with Topology Driven Flylines
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Data Flow Analysis/DFA is commonly used as tool for early floorplan feasibility analysis, including optimizing macro and port placements in the context of the data flow. However, richer visualization techniques are necessary for high speed structured data-paths and mixed signal designs with structured wire/bus topologies. To better understand the impact of major data flow busses and critical signals topologies on macros placement, we introduced a concept of topology driven intelligent fly-lines. We utilize annotation objects to draw the fly-lines on the canvas. Using an intuitive GUI, users can define numerous types of routing topologies (I, L, T, Z, F, stair-case) combined with constraints like bussing, interleaving and shielding. By specifying nets and/or busses and desired topologies to connect pins/ports of the specified nets, users can see how desired routing would affects macro placement making it easier to optimize the placement. The topology-driven fly-lines can be quickly redrawn to allow different topologies to be displayed providing what-if scenarios to speed-up floorplan feasibility exploration. Finally, we show the application of this feature on a block with complex topologies and the productivity improvements provided by this feature.
Synopsys Tools Used:
IC Compiler
Target Audience:
Advanced |
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| D1 Tutorial Session - Scan Compression |
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Understanding Compression - Past, Present, and Future
Rohit Kapur - Synopsys |
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Scan compression has been commercially available since the year 2000. Rapid adoption of the technology drove rapid changes in the needs and solutions. This presentation will talk about the changing compression technology relative to the changing user environments. The current state of the art compression technology will be presented with a direction on the future changes that will be seen. |
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Achieving High Compression Ratios with Cell-Constrained Designs Using DFTMAX Ultra
Anand Gangwar - Synopsys; Kalyana Kantipudi - Altera |
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The size and number of hardened IPs in FPGAs is growing every generation. Unlike traditional IPs, these IPs perform different functions and operate in multiple modes. This is achieved by special control registers which are spread throughout the IP. These control registers are part of the scan chains and need to be constrained during ATPG. With a high internal chain to scan input ratio, it becomes difficult for the ATPG tool to satisfy the cell constraints due to datadependency among the scan cells. In this paper we describe our migration from the existing test methodology to DFTMAX Ultra. Apart from the benefits of DFTMAX Ultra like modular test development, high output compression ratio, package based testing without pattern regeneration and minimal pattern overhead, we explain in details how the DFTMAX Ultra codec architecture was optimized to handle large number of scan cell constraints, with virtually no test QoR impact. |
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| E1 Panel & Demo Session - VCS AMS Verification |
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Tackle Mixed-signal Verification Challenges From Block-level Design to Complex SoCs With VCS AMS
John Brennan - Cavium; Helene Thibieroz, Warren Anderson - Synopsys |
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From simple co-simulation at the block level to complex SoC verification, mixed-signal verification is everywhere today. In addition to a universal need for superior performance and ease of use, challenges may rise from simple connectivity problems to more complex interferences between analog and digital data blocks, various behavioral models requirements and/or the capability to extend low power across boundaries. A mixed-signal verification solution must offer not only high performance but also superior functional verification technologies that address those challenges.
During this panel, experts from Cavium, Intel and Synopsys IP group will present VCS AMS usage and flow for their specific designs and discuss what the best approaches are to tackle today and tomorrow mixed-signal verification.
Synopsys Tools Used:
VCS, CustomSim, FineSim
Target Audience:
Digital and custom verification and design engineers/managers involved and interested in mixed-signal simulations |
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Demonstration of New VCS AMS Concepts
Maureen Ladd - Synopsys |
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A demonstration and presentation of recent improvements in the VCS AMS flow, based on Synopsys provided tutorials. This will help jump-start any user interest in improving their mixed-signal productivity with the advanced concepts discussed in the panel session.
Synopsys Tools Used:
VCS, CustomSim, Custom WaveView, Verdi
Target Audience:
Digital and custom verification and design engineers/managers involved and interested in mixed-signal simulations |
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| F1 User Session - System Integration and Design |
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PDSparc - A Drop-In Replacement for LEON3 Written Using Synopsys Processor Designer
David Whelihan, Ph.D., Kate Thurmer - MIT Lincoln Laboratory |
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Microprocessors are the engines that drive the modern world. For decades this space has been dominated by large manufacturers, such as Intel and AMD, which design and fabricate a range of stand-alone processors. However the proliferation of small computing devices such as cell phones, laptop computers, and internet-enabled appliances has opened a significant new niche: the Application Specific Standard Product (ASSP) microprocessor. These processors usually start out as soft-cores that are parameterized at design time to realize exclusively the specific needs of the application. The microprocessor is a small part of a working system and requires peripherals such as DRAM controllers and communication sub-systems to properly carry out its function. Therefore, creating a full system requires significant top-level integration.
This work introduces PDSparc, an ASSP based on the OpenSparc architecture. PDSparc was generated using the Synopsys Processor Designer (PD) tool, which enables detailed specification of a pipelined processor using a C-like language called LISA [13]. PDSparc replaces a LEON3 processor, a derivative of the Sparc v8 microarchitecture [5], in a full synthesizable SoC system [3] provided by Cobham Gaisler under the Gnu Public License. This integration required significant reverse engineering of the provided cache interfaces, and was facilitated by a novel socket-based debug interface to the PDSparc simulation model. This debug interface greatly accelerated system development by permitting micro-stepping of the PDSparc processor code in synchronization with the peripheral and bus package running on a commercial RTL simulator.
We anticipate that this paper will be of interest to the practitioners in the field who can use the approach and the lessons learned described in the paper in building their own processor execution cores.
Synopsys Tools Used:
Processor Designer
Target Audience:
Intermediate |
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AMBA Interconnect Design Flow Automation
Tom Ajamian - Analog Devices |
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A system architect faces many challenges when designing an AMBA-based interconnect for an SoC. Gathering requirements, creating specifications, and then taking those specifications and turning them into a cohesive design that matches requirements for performance, power and area (PPA) is not straightforward. Quantifying PPA is essential in tuning the design for the requirements. While traditional pencil and paper or spreadsheet methods have been used for PPA estimates, these approximations fall short for tuning and not overshooting the performance of the design. Tools such as Synopsys' Platform Architect and its Interconnect and Memory Subsystem Optimization (IMPO) flow help provide a solution to quantifying performance; however closing the loop between specification and design using ARM's AMBA Designer and Platform Architect modelling can require manual translation. We propose a more automated flow, from specification creation to design to performance analysis that allows for the specification to be the sole data source for all stages saving considerable time and reducing the potential for error introduction.
Synopsys Tools Used:
Synopsys Platform Architect IMPO (Interconnect and Memory Hierarchy Performance Optimization)
Target Audience:
Intermediate |
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Thursday, September 24, 2015
1:15 PM - 3:15 PM |
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| A2 User Session - Adaptability of UVM in Complex Environments |
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Customization of RAL Adapters and Predictors in UVM 1.2
Steven K. Sherman - AMD |
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This paper reviews lessons learned in customizing RAL adapters and predictors. This includes a brief overview of provided examples and options per UVM reference and user guide. It continues with motives, strategies and customizations used in a real verification environment.
Synopsys Tools Used:
UVM 1.2
Target Audience:
Intermediate |
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Customizing UVM Report Server (UVM 1.1d, UVM 1.2)
Kaushal Modi - Analog Devices |
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It is a recommended practice that the UVM reporting macros 'uvm_info, 'uvm_warning, 'uvm_error and 'uvm_fatal be used for displaying messages with corresponding severities, instead of the traditional Verilog $display. The uvm_report_server class is a global server that processes the reports generated by the above macros. A user can extend this class, add customization and use that instead of the default report server to display messages with better readability in real time by using techniques like message re-ordering, removal of redundant text, line wrapping, indentation and use of terminal colors. This paper explains the motivation and implementation of such a custom report server in both UVM 1.1d and UVM 1.2.
Synopsys Tools Used:
The suggested technique in the paper is vendor-agnostic. It applies equally well to a Synopsys user developing/debugging a UVM test bench. Synopsys VCS was used for the simulating UVM 1.1d and UVM1.2 based test benches.
Target Audience:
Intermediate |
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Lies My Teacher Told Me About The UVM - Basic Stimulus
Justin Refice - NVIDIA |
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Many users of the Universal Verification Methodology purchase books and other training materials which offer a simple description of how to setup your first testbench. These materials unfortunately tend to over-simplify, providing easy-to-read answers which scale poorly, provide minimal potential for reuse, and often omit important functionality.
This paper will demonstrate where the common view of stimulus breaks down and where the hazards in the simplified examples lie. Additionally a better approach will be presented leveraging familiar concepts from networking models, starting with a new perspective on the lowly sequence item.
Synopsys Tools Used:
UVM
Target Audience:
Intermediate |
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| B2 Tutorial Session - Synthesis & Power Analysis |
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UPF-Based Synthesis Flow for Complex Mixed Signal IP Blocks
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Low power architecture for mixed signal IP blocks presents unique challenges with UPF methodology and implementation. Special requirements in UPF representation of analog supplies, modeling of derived supplies, related supplies and their interaction with the SoC need to be taken into consideration. The hierarchical multi-instance nature of mixed signal IPs adds additional complexity in RTL and UPF coding.
In this paper we describe the implementation of UPF 1.0 based flow to a mixed signal IP design. We cover the design changes needed with RTL, UPF, macro and library collateral to successfully implement a full UPF based flow. We describe the power domains, isolation and level shifter strategy as well its implications on physical design. Finally, we go over the lessons learned from our experience and future enhancements needed to improve the methodology.
Synopsys Tools Used:
Design Compiler, IC Compiler
Target Audience:
Advanced |
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Clock Design Challenges in a Large, Low-Power, High-Speed Signal Processing Design
Rishi Yadav, Nimit Nguansiri - The MITRE Corporation |
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Switching activity from RTL simulations has become the most common source of activity to use for power analysis. Compared to gate-level (GL) simulation, this activity is preferred for several reasons, i.e. RTL activity is faster to produce, is more commonplace due to its use for RTL development and verification, and it produces smaller file sizes. It is however, more difficult than GL activity to employ for post-synthesis and post-physical-design power analysis. For example, names in the activity file do not match post-implementation netlist names and new objects and structures have been introduced into the design since RTL, such as feedthroughs for blocks, multi-bit registers, BIST logic, clock and power gating. Additionally RTL simulation may not include the activity for new, implementation-introduced signals, including scan-mode, scan-in, power-on/off, etc. Other complexities include the simulation activity has memories or logic configured differently than what is required for the power analysis.
This paper will describe how the PT-PX Cycle Accurate Peak Power (CAPP) power analysis engine handles activity annotation and propagation. We'll describe basic debug skills and more specific skills that helped lead us to discover propagation and power calculation errors in our testbench. Workaround methods, fixes and strategies are then detailed for each.
Synopsys Tools Used:
PrimeTime PX
Target Audience:
Intermediate |
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Accurate Time-Based Power Analysis on a Complex Design Using RTL Simulation Activity
James Lee - Qualcomm |
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Switching activity from RTL simulations has become the most common source of activity to use for power analysis. Compared to gate-level (GL) simulation, this activity is preferred for several reasons, i.e. RTL activity is faster to produce, is more commonplace due to its use for RTL development and verification, and it produces smaller file sizes. It is however, more difficult than GL activity to employ for post-synthesis and post-physical-design power analysis. For example, names in the activity file do not match post-implementation netlist names and new objects and structures have been introduced into the design since RTL, such as feedthroughs for blocks, multi-bit registers, BIST logic, clock and power gating. Additionally RTL simulation may not include the activity for new, implementation-introduced signals, including scan-mode, scan-in, power-on/off, etc. Other complexities include the simulation activity has memories or logic configured differently than what is required for the power analysis.
This paper will describe how the PT-PX Cycle Accurate Peak Power (CAPP) power analysis engine handles activity annotation and propagation. We'll describe basic debug skills and more specific skills that helped lead us to discover propagation and power calculation errors in our testbench. Workaround methods, fixes and strategies are then detailed for each.
Synopsys Tools Used:
PrimeTime PX
Target Audience:
Intermediate |
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| C2 Tutorial Session - ICC II and ARM Place & Route |
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ICC II Marketing and R&D Update
Stelios Diamantidis, Henry Sheng - Synopsys |
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In its first year since introduction, IC Compiler II has proven to be a true game-changer in the world of physical design, accelerating silicon success for some of the world's most advanced ICs. Please join us as we take a look at the many innovative technologies in IC Compiler II and learn how market leaders are taking advantage of faster throughput to transform product development, opening up a world of new opportunities.
Synopsys Tools Used:
IC Compiler II
Target Audience:
IC Compiler, IC Compiler II users |
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ICC II Technical Highlights and User Experience
Joe Varghese - Synopsys; Zhong Chen, Bill Stysiack, Najam Zaman - Cavium |
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Efficient optimization is a necessary, yet challenging aspect of the physical implementation flow. IC Compiler II and the underlying physical optimization engines have been re-thought and re-architected to address these growing challenges. This presentation will focus on the technical highlights of IC Compiler II and also some user experience snippets from successful usage of IC Compiler II to tape out deep submicron designs.
Synopsys Tools Used:
IC Compiler II
Target Audience:
Physical design engineers |
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High-Performance, Energy-Efficient Implementation of the ARM Cortex-A72 Processor Using Synopsys IC Compiler and IC Compiler II Place-and-Route Systems
Joe Walston - Synopsys |
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This is a joint tutorial by ARM® and Synopsys. We will start by sharing the ARM processor roadmap and ecosystem and the strong ongoing ARM-Synopsys collaboration. You will learn about ARM's latest ARMv8 architecture based Cortex®-A72 processor, its performance, power and area goals and the target markets.
We will discuss engineering trade-offs and the flow development process to balance gigahertz+ performance and low power on an ARM Cortex-A72 processor core implementation. This tutorial will highlight best practices and enabling technologies from Synopsys' IC Compiler place and route system to meet challenging performance targets, while minimizing dynamic and leakage power. Synopsys' high-performance core (HPC) methodology will be demonstrated through a Reference Implementation of an ARM Cortex-A72 processor core with ARM Artisan® POP™ libraries and memories for core-hardening acceleration on TSMC's 16FF+ process. Implementation highlights include strategies for an optimal gated clock network implementation, area optimization and TNS management across the flow for power savings, and maintaining flow correlation to balance timing and power. 16FF+ route considerations, modeling advanced on-chip variation effects and advanced cross-talk reduction techniques address key process technology careabouts. The session will end with an overview of the significant turnaround time benefits achieved on the Cortex-A72 processor using IC Compiler II, Synopsys' next generation place & route system.
Synopsys Tools Used:
Synopsys IC Compiler and IC Compiler II Place-and-Route Systems
Target Audience:
Physical designers using Synopsys Place & Route tools like IC Compiler and IC Compiler II |
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| D2 Tutorial Session - Technology |
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Lowering DPPM through Advanced Fault Models
Don Skinner - Synopsys |
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This tutorial will describe how cell aware slack based test can lower DPPM.
Synopsys Tools Used:
TetraMAX
Target Audience:
Test and manufacturing engineers |
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Auto LBIST
Don Skinner - Synopsys |
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This tutorial will overview Synopsys' new Automotive LBIST solution.
Synopsys Tools Used:
DFT Compiler, DFTMAX, TetraMAX
Target Audience:
DFT engineers |
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SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System
Mike Ricchetti - Synopsys |
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System-on-chip (SoC) test becomes significantly more complex as designs become larger and the amount and variety of IP used increases. Today's SoCs present a unique set of test challenges, including higher test costs, higher power consumption during test, lower design productivity, and new defects at small geometries (FinFET). There will be an update on new features and capabilities of the DesignWare STAR Memory System, Synopsys' memory test, repair, and diagnostics solution. In addition, we will describe the unique capabilities of the DesignWare STAR Hierarchical System, a hierarchical test solution for all IP/cores on your SoC including interface IP, analog/mixed-signal IP and digital logic blocks.
Synopsys Tools Used:
DesignWare STAR Memory System, DesignWare STAR Hierarchical System
Target Audience:
Designers, DFT engineers, test engineers, product engineers, and foundry engineers who are or will be designing or characterizing SoCs. The presentation will provide introductory as well as advanced content. |
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| E2 Tutorial & User Session - Layout & Simulation Productivity Improvements |
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Getting to Simulation Results Faster with StarRC
Al Blais - Syopsys |
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This presentation will cover some of the latest transistor level improvements in StarRC, including runtime, netlist size and other productivity improvements. The latest technology trends and their impact on parasitic extraction will also be discussed.
Synopsys Tools Used:
StarRC
Target Audience:
Custom design and layout engineers and managers who would like to improve extraction productivity and prepare for the next process node |
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Navigating the SPICE Continuum
David W. Winston - IBM |
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Since the 1970s, SPICE-type circuit simulators have helped designers understand circuit performance at the transistor level. The growing size and complexity of integrated circuits led to the development of "FastSPICE" tools in the 1990s. These tools allow designers to sacrifice accuracy in exchange for faster simulation run time and increased circuit size. However, within the last ten years, considerable overlap has developed between SPICE tools and FastSPICE tools - SPICE tools have "accelerated" modes and FastSPICE tools have "SPICE" modes. A veritable continuum of accuracy versus speed now exists amongst all of the simulation tools on the market. This paper will help the EDA professional navigate the current state of the art of circuit simulation tools. It will examine the challenges that tool developers face while providing useful techniques and recommendations for evaluating circuit simulation offerings.
Synopsys Tools Used:
HSPICE, FineSim, CustomSim, WaveView
Target Audience:
Intermediate |
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Need to Simulate SPICE Netlists? Have I Got a GUI for You!
Dave Chou - Synopsys |
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This tutorial will introduce the audience to the Synopsys SPICE simulation environment, a graphical environment for running Synopsys circuit simulators. The presentation will walk through a set of features with particular emphasis on post-processing.
Synopsys Tools Used:
Synopsys SPICE Sim Env, HSPICE, CustomSim, Custom WaveView
Target Audience:
Custom designers interested in increasing productivity and utilizing new techniques to manage simulations and analysis |
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| F2 Tutorial Session - FPGA Prototyping and Design |
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Recent Developments in High Reliability Design Techniques for FPGA
Carl Cleaver - Synopsys |
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High reliability design techniques (High Rel), used to make FPGA's tolerant of radiation faults, are becoming critical in both commercial and mil-aero arenas. This is due in part to the shrinking geometries offered by present high density FPGA's. Automation of High Rel techniques can aid designers in achieving fault tolerance. This tutorial will discuss the current state of techniques available, methods by which they can be automated, and their suitability for different classes of FPGA fabrics.
Synopsys Tools Used:
Synplify Premier
Target Audience:
FPGA designers and verification engineers |
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Incorporating UPF Specifications and Equivalence Checking into your FPGA Prototype
Steven Gercken - Synopsys |
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Developing an FPGA prototype flow using ASIC specifications & techniques can improve the accuracy and verity of the FPGA prototype. ASIC specifications can include Unified Power Format (UPF) information to define the implementation of power control structures. Those power control structures can be implemented in an FPGA prototype for verification. The information provided by UPF, including power domain specification, isolation cell strategies, and retention logic modeling, will be compared between FPGAs and ASICs. ASIC design transformations are verified using formal equivalence checking. Likewise, formal equivalence checking can be useful for FPGA Prototype developers.
This two part tutorial examines the benefits of applying Unified Power Format (UPF) functionality from your ASIC design flow into the FPGA synthesis process.
Synopsys Tools Used:
HAPS, ProtoCompiler
Target Audience:
Verification, validation, software engineers |
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Multi-FPGA Prototyping of Over 1.5 Billion ASIC Gates
Troy Scott - Synopsys |
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FPGA-based prototyping is popular because it provides an economical way to functionally validate an SoC design by creating a prototype that runs "at speed" and includes real world I/O, enabling early software development, HW/SW integration, and system validation. Experienced engineers are familiar with its benefits but still face challenges of scalability to support large capacity designs, prototype development taking too long, and once they have a working prototype it's too hard to debug. The session presents Synopsys' new fully integrated next generation FPGA-based prototyping solution utilizing the latest Xilinx Virtex UltraScale FPGA's supporting 1.6 Billion ASIC gates with the highest multi-FPGA performance combined and built-in high visibility debug.
Synopsys Tools Used:
HAPS, ProtoCompiler
Target Audience:
Verification, validation, software engineers |
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Thursday, September 24, 2015
3:30 PM - 5:00 PM |
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| User Session - Optimizing Your Verification Environment |
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Using Certitude Efficiently
Shahid Ikram, Craig Barner, Joseph D'Errico, and Jim Ellis - Cavium; Marty Rowe - Synopsys |
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We present a light-weight methodology for Certitude usage. The methodology provides a set of guidelines defined by the constraints of a design verification environment. These guidelines are facilitated through a turnkey process to incorporate Certitude in the design verification environment. The turnkey process is fully automated and reduces the Certitude setup time for a new design to less than an hour and down to few minutes for incremental changes in a design environment already setup for Certitude. The next important piece was to restrict our attention to the top three fault classes. It saved us debugging time without affecting other activities. The final piece of our methodology was the statistical tracking of the quality through ComputeMetric. This metric was used in conjunction with other standard metrics to track the design verification progress. The metric was also used for test suites grading and comparing the quality of regression suites against exerciser suites.
Synopsys Tools Used:
Certitude, VCS
Target Audience:
Intermediate |
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Developing C++ Testbench Components Using UVM Phase and Agent Concepts
JinHaeng Cho, Scot Hildebrandt - NVIDIA |
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The UVM provides many useful libraries and as such is becoming the new de facto testbench standard. A majority of new testbench development adopts UVM and many companies want to convert non-UVM testbenches to UVM. However converting non-UVM testbenches into UVM may not be cost effective due to various reasons such as: legacy infrastructure, familiarity of language, external IP support, etc. Also many companies are using C++ to develop architectural or proof of concept models before the actual design phase starts and it is desirable to reuse those C++ model in the design verification environment. This paper introduces a technique on developing C++ testbench components using the UVM phase and agent concepts. This approach makes it easier not only to reuse such C++ models in the design verification phase but also to convert them into UVM components. This method also has the advantage over a pure UVM testbench in terms of fast experimental turnaround time created by reduced simulator compile time.
Synopsys Tools Used:
VCS
Target Audience:
Intermediate |
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| B3 User Session - Technical Committee Best Papers from SNUG Europe |
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Advanced Synthesis Technique Using Target Library Subset
Laurent Besson - STMicroelectronics |
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Over the last few years, Design Compiler has introduced the notion of target library set per instance, as opposed to traditional target library set for the whole design. Using this quite new feature is allowing a better guidance of synthesis and helps in the following fields: leakage recovery for low-power design, constant propagation through dont_touch cells and cells mapping on clock path. This paper intends to demonstrate the usage and benefit on these different fields seen on a Low-power SoC design done in 28nm-FDSOI technology and how it helps to gain 20% on power leakage.
Synopsys Tools Used:
Design Compiler, Design Compiler Graphical
Target Audience:
Medium to advanced synthesis users |
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MTCMOS Based Low Power Implementation in GLOBALFOUNDRIES 28nm Process Using UPF2.0 - A Case Study
Ramin Navai - Synopsys; Farid Labib - GLOBALFOUNDRIES |
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Challenges in today's complex low power designs need methodologies that ease the power intent specification, implementation, and verification process. The IEEE 1801-2009 standard (UPF2.0) supports a more abstract and user friendly way to accomplish this task. In this paper we present a use case study for applying UPF2.0 in the implementation process of a RISC processor core in a 28nm node. For this case study, an MTCMOS based on-chip switching approach was chosen. Two variants, array and ring based approach, are discussed in the paper. Solutions for the discovered issues in the Synthesis and P&R flow are presented as well.
Synopsys Tools Used:
Design Compiler, Design Compiler Graphical
Target Audience:
Medium to advanced synthesis users |
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| C3 User & Tutorial Session - ICC II |
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Investigating the Next Generation Place and Route Tool
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The next generation of place and route tools have been architected with modern design challenges in mind. Providing greater capacity and much faster algorithms, larger design sizes can now be handled before needing to consider hierarchical methodologies. As a consequence, designer productivity has vastly improved. This paper discusses the complexities seen when taking a large design on an advanced technology node through placement and route using the latest place and route technology. It will pay particular attention to the analysis of the timing results by comparing them to the legacy place and route tool. It will also discuss if it lives up to the expectation of being 10x faster on a partition with extremely long runtimes.
Synopsys Tools Used:
IC Compiler II
Target Audience:
IC Compiler, IC Compiler II users |
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Getting Productive in the ICC II GUI
Dan Guilin - Synopsys |
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IC Compiler II provides significant improvements in ease of use and productivity for today's chip designs, with improvements in productivity, simplicity, and performance. This tutorial will focus on the new features provided in two key areas of the interactive solution to help you get productive with the new environment. We will start out with an overview of the interactive design environment (IDE) focusing on features to help you find the functions you need, manage the views of the data, and organize the environment in a way that is customized for your use. Secondly we will focus on the tools provided to create and edit your design, along with capabilities that enable dynamically updated analysis of the changes. After the tutorial you will be able to start exploring and using the interactive environment for IC Compiler II.
Synopsys Tools Used:
IC Compiler II
Target Audience:
Physical designers |
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| D3 Tutorial Session - Introducing Synopsys SpyGlass |
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Introduction to Synopsys SpyGlass
Al Joseph - Synopsys |
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Introduction to SpyGlass DFT ADV
Al Joseph - Synopsys |
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This tutorial will provide an overview of the SpyGlass DFT ADV, which provides analysis of testability on RTL.
Synopsys Tools Used:
SpyGlass
Target Audience:
RTL and DFT engineers |
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Introduction to SpyGlass Power
Al Joseph - Synopsys |
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This tutorial will provide an overview of the SpyGlass Power, which provides a solution for exploring RTL for power reduction opportunities and characterizing power reduction efficiencies of what is already coded in the RTL.
Synopsys Tools Used:
SpyGlass
Target Audience:
RTL, Power and Verification |
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| E3 User & Tutorial Session - Efficient Transistor Level implementation |
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EDA Flow for a Power-Efficient Microprocessor Using iPDK Created from Non-Interoperable oaPDK and Modified Synthesis to Support Asynchronous Logic
Bill Ellersick - Analog Circuit Works; Dylan Hand - Reduced Energy Microsystems; Peter Berell - University of Southern California |
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The EDA flow used in the development of a Power-Efficient Microprocessor is presented, focusing on two challenges. The first challenge was to enable transistor level design, simulation and layout in the desired process by creating an Inter-operable iPDK from a non-interoperable oaPDK with proprietary (non-Synopsys compatible) code in schematic callbacks and layout Pcells. Risks were mitigated with LVS, DRC and PEX flows that were fully compatible. The second challenge was modification of the synthesis flow to support asynchronous logic that provides more than 3x reduction in power vs. synchronous implementation.
Synopsys Tools Used:
Full Synopsys flow
Target Audience:
Custom design and layout engineers, as well as integration engineers that are involved in custom and ASIC flows |
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Achieving Productive Custom Layout When Using FinFET Devices
Nicolas Regis – Synopsys |
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Users who make the best use of the tools and methodologies can substantially reduce the time it takes to create hand-crafted layout. In this presentation, we discuss the most important layout challenges presented by FinFET process nodes. We'll review the new features that were added for dealing with FinFETs and provide tips for how to maintain high layout productivity for any process node. We'll also take a deeper look at one of the key challenges facing FinFET designers – how to find and resolve EM issues
Synopsys Tools Used:
Custom Designer
Target Audience:
Custom design and layout engineers and managers who would like to improve extraction productivity and prepare for the next process node. |
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| F3 User Session - HW Emulation |
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Enabling Greater Reliability, Scalability, and Flexibility of GPU Emulation with a Hybrid Virtual Machine Based Approach
Alex Starr - AMD |
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In an effort to reduce time to market while increasing hardware and software quality, GPU designs use hardware emulation to “shift left” traditional post-silicon activities to a pre-silicon environment. Typical configurations have a full speed PC, running the system software, OS, and driver, physically connected with in-circuit custom hardware bridges to a hardware emulator containing the GPU design. This has benefits of enabling high-speed software execution while interacting with the real RTL design in the emulation system; however, as the usage of emulation increases, new challenges of reliability, scalability, and flexibility are emerging.
This paper discusses AMD's development of a new approach utilizing ZeBu Server 3 emulation hardware with a VirtualBox virtual machine and ZeBu PCIe transactor based hybrid environment, which paves the way to increasing reliability, scalability, and flexibility aspects while crucially maintaining the key performance requirements and end user use model from the traditional in-circuit approach.
Synopsys Tools Used:
ZeBu Server 3, ZeBu PCIe transactor
Target Audience:
Advanced |
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Multi-Platform Continuum: ZeBu to Post-Silicon …. and Back
Al Czamara - Test Evolution |
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Taking tests developed in pre-silicon and using them in post-silicon is limited to either internal CPUs, or simple vector-capture and playback. Debugging issues found in post-silicon on pre-silicon platforms is almost too painful to endure. We will present an extension of the verification continuum from pre-silicon to post-silicon using PCIe Gen3.1 as an example, showing a seamless path between ZeBu and post-silicon platforms, including the use of the PCIe HAPS IP prototyping kit as an aid in our development.
Synopsys Tools Used:
Zebu, HAPS
Target Audience:
FPGA designers and verification and software engineers |
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| Publish Only |
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Checking Typos in Simulation Command Line Plusargs
Thinh Ngo - Broadcom |
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Modern tests are configured internally via constrained random configuration objects and externally via simulation command line plusargs. Various test intents and verification effects are realized via this combined approach. Typos in plusargs can completely void the intended test configurations and verification effects resulting in false passes and unverified features. Therefore, it is important to check the plusargs associated with each test and to fail the test if they are mistakenly specified. The following procedure can be used to implement such a checker:
- Store the expected plusargs used inside every test by creating/calling a function to register each expected plusarg
- Retrieve the plusargs used by every test during simulation by calling uvm_cmdline_processor.get_args
- Check that the plusargs used by every test match the expected plusargs stored in step 1 otherwise fail the test.
Synopsys Tools Used: VCS Target Audience: Intermediate |
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