In this workshop you will learn to perform Static Timing Analysis (STA) using PrimeTime by executing the appropriate high-level summary reports to initiate your analysis, customizing and interpreting detailed timing reports for debugging, and exploring and analyzing the clocks that dictate STA results.

Within PrimeTime you will debug STA constraints that may be either incomplete or incorrect which cause invalid timing violations or result in hiding real timing violations.

You will also learn to maximize your productivity by validating inherited scripts for your design, by creating scripts using a Synopsys recommended methodology, by identifying opportunities to improve run time, and by customizing your environment for ease of running and debugging.

The workshop includes comprehensive hands-on labs, which provide an opportunity to apply key concepts covered during the lectures.


At the end of this workshop the student should be able to:

  • Generate summary reports for design violations organized by clock, by slack, by timing check, or by where they occur on either boundary paths or register-to-register paths.
  • Interpret violation details, both for netlist and for constraints, in a timing report for setup and hold, recovery and removal, clock-gating setup and hold, data to data setup and hold, and minimum pulse width
  • Generate timing reports for specific paths and with specific details
  • Find and debug constraint issues that may cause invalid timing violations or hide real ones
  • Validate, confirm, debug, enhance, and execute a PrimeTime run script
  • Create a PrimeTime run script based on a recommended methodology
  • Identify opportunities to improve run time
  • Create a saved session and restore a saved session
  • Identify the clocks, where they are defined, and which ones interact, on an unfamiliar design
  • Determine when and how to use path-based analysis (PBA)

Audience Profile
ASIC digital designers, or verification engineers, who will be using PrimeTime to perform Static Timing Analysis (STA) on pre- or post-layout gate level designs, and who need to validate STA constraints for correctness and completeness.

To benefit the most from the material presented in this workshop, students should:

  • Have a basic understanding of digital IC design
  • Understand elements of gate level design: chip vs. block level, sequential vs. combinational logic, clock tree vs. data path, pre- vs. post- layout differences
  • Have familiarity with UNIX and a UNIX text editor of your choice

Course Outline

Day 1: Generating Reports

  • Generating Setup and Hold Reports
  • Interpreting Timing Arcs in Reports
  • Generating Timing Paths of Interest
  • Reporting Four Additional Checks
  • Generating Summary Reports

Day 2: Constraining for Static Timing Analysis

  • Constraints in a Timing Report
  • Identifying Constraint Issues
  • Constraining Multiple Clocks
  • Debugging Constraint Issues

Day 3: Static Timing Analysis Flow and Best Practices

  • Timing Analysis Flow
  • Analyzing Four Specific Situations
  • Path-based Analysis
  • Best Practices for STA in PrimeTime

Synopsys Tools Used

PrimeTime 2016.06-SP2