The DesignWare® STAR Hierarchical System is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores, including analog/mixed-signal IP, digital logic cores and interface IP. It significantly reduces test integration time by automatically creating a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level, and increases test quality of results (QoR), including optimizing test time and power through flexible test scheduling of IP and cores. It simplifies SoC test pattern creation by using the IEEE 1500 network to port IP or core-level patterns to the SoC-level, and allows silicon debug and diagnostics by enabling the IP debug test modes from the SoC level. The STAR Hierarchical System is compliant with IEEE 1687, which allows re-use of embedded test instruments for system-level debug. The system’s highly automated design-for-test (DFT) implementation and hierarchical IP and core-level test enables engineering teams to cut their test integration time to a matter of days and bring their designs to market faster and with lower design and test costs.
The STAR Hierarchical System incorporates process and clock monitoring capabilities as part of the Measurement Unit (MU). Clock integrity is an important safety concern for automotive, aerospace and industrial applications. The ability to measure the clock frequency and duty cycle is critical requirement for these applications.
SoC designers and silicon aggregators targeting automotive, IoT, enterprise, and consumer applications licensed STAR Hierarchical System with the added flexibility of consulting services for hierarchical test planning, generation, insertion, and verification for logic, analog, mixed-signal, and PHY IP blocks.
DesignWare STAR Hierarchical System Datasheet
DesignWare STAR Hierarchical SystemThe STAR Hierarchical System is a new automated hierarchical test solution that reduces test integration time and improves test QoR for SoCs.
Fellow and Chief Architect, Solutions Group, Synopsys
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- Hierarchical test accelerates SoC testing
- Automated test integration and validation of all IP/cores on SoC increases design and DFT productivity
- Flexible IP/core test scheduling optimizes test time and power
- Automated porting of IP/core patterns to SoC-level enables reuse of test patterns
- Optimized hierarchical IEEE 1500 network reduces area and signal routes
- Efficient on-chip e-fuse programming for IP calibration/trimming
- Certified to support the ISO 26262 ASIL D standard for automotive functional safety