Manmeet Walia, Synopsys | April 21 | 10:00 a.m. – 10:25 a.m.
The increasing volume of data for AI workloads is driving the need for more advanced networking functionality for faster data movement. SoCs for hyperscale data centers, artificial intelligence, and networking applications are more complex. Such SoCs are disaggregated in a multi-die package, requiring a robust and reliable 112G USR/XSR or HBI links to allow inter-die connectivity. In this session, we will describe the new use cases, such as co-package optics, for die-to-die connectivity as well as outline key design requirements of standards-based SerDes and parallel die-to-die interface solutions with testability and performance/power tradeoff capabilities and supporting interposer and substrate technologies for 2.5/3D packaging.
Gary Ruggles, Synopsys | April 21 | 10:25 a.m. – 10:50 a.m.
In this session we will outline some of the considerations that designers must be aware of when they are ready to shift their designs to PCIe 6.0: such as doubling of the data rate, accessing a complete IP solution that offers optimized performance and seamless interoperability between the controller and PHY, achieving timing closure at 1+ GHz, and understanding the impact of the new PCIe 6.0 features including FLITs, new low power state, and PAM-4 signaling.
Licinio Sousa, Synopsys | April 21 | 11:00 a.m. – 11:25 a.m.
Accurately estimating power for vision SoCs can make the difference between success and a multi-million-dollar failure. Estimating power can be fairly straightforward for a RISC processor, but vision SoC designs include neural networks with intense computation requirements making accurate power estimation more complicated. How can a designer have confidence in the power estimations to deliver a product that meets the design requirements? Is the QoR representative of the end product power consumption? Applications used for power analysis can have a big impact on the QoR. Avoiding the pitfalls of inaccurate power estimation that are specific to vision SoCs can improve your SoCs success. This presentation will cover the advantages and disadvantages of methodologies used for power estimation and verification for AI-enabled vision SoCs. Itll discuss ways estimation tools falter when applied to vision neural networks and propose a methodology to uncover the most accurate estimations from vendor selection through tapeout.
Brett Murdock, Synopsys | April 21 | 11:25 a.m. – 11:50 a.m.
HBM DRAMs, mainly for GPUs and accelerators, provide high throughput per channel at a low power per bit transferred. For applications seeking higher memory density and bandwidth than HBM2E, the industry is now anticipating the release of next-generation HBM3 which is expected to provide higher transfer rates with even better performance. In this session, we will focus on the introduction of HBM3 which is expected to double the density to 64GB/s with 512 GB/s of bus size, all essential requirements for high-performance computing.
Stephen Crosher, Synopsys I April 21 | 12:00 p.m. – 12:25 p.m.
The latest SoCs on advanced semiconductor nodes especially FinFET, typically include a fabric of sensors spread across the die and for good reason. But what are the benefits? This presentation explores some of the key applications for in-chip sensing and PVT monitoring and why embedding this type of IP is an essential step to maximise performance and reliability and minimise power, or a combination of these objectives. The presentation will also examine use cases from key application platforms including AI, Data Center, Automotive, 5G and Consumer.
Pankaj Kumar Dubey, Samsung Electronics | April 21 | 12:25 p.m. – 12:50 p.m.
Due to shrinking silicon process nodes, transistors are getting smaller and smaller making SoC subject to failures due to external disturbances (EMI, heat, power surges etc.). As a result, SoC designers who use PCIe as the main communication interface in their SoCs are looking for ways to bulletproof their design by implementing advance Reliability, Availability and Serviceability (RAS) mechanism. DesignWare controller includes a set of RAS DES features which can make debugging much simpler but unfortunately is unexplored. In this paper, some of the potential PCIe hazards faced by SoC designers and SoC application users are explained. This paper also showcases the implementation and usage of proposed PCIe RAS DES framework in the Linux subsystem. The proposed framework highlights the detection, recovery and prevention of those hazards without use of any expensive hardware based PCIe analyzers.
Ron Lowman, Synopsys I April 20 | 12:25 p.m. – 12:50 p.m.
The demand for neural network processing is requiring SoC hardware innovation across all market segments. These demands bring a new set of IP requirements unique to different segments, including new processors, higher bandwidth memories, high speed interconnect, and optimized architectural configurations. Constantly evolving next-generation neural networks place unique additional demands over and above the standard PPA needs of traditional chipset hardware. This presentation will describe how a leading AI SoC customer supports emerging requirements for fast-changing neural networks. Attendees will learn about successful implementations of how IP, IP tools, and design services can enable more competitive, higher performance SoC designs while minimizing time-to-market.
Filip Moerman, Bosch I April 20 | 8:00 a.m. – 8:25 a.m.
Convolutional Neural Networks (CNN) are widely adopted for various computer vision tasks. They are also gaining traction in the auto-motive industry. As such, front-view cameras may rely on CNNs for semantic segmentation and object detection. They typically require very performant and very efficient CNN accelerators. The presentation will give a brief overview of CNNs in general. It will explain the use of CNNs for semantic segmentation and object detection and describe some CNNs designed for these tasks. It will discuss the challenges of embedding a CNN accelerator in a SoC and of providing a SW tool chain that enables the full performance and efficiency of the CNN accelerator. It will describe the performance results generated by Bosch using Synopsys' DesignWare ARC EV processor and CNN engine with 3520 MACs.
Vladimir Litovtchenko, Synopsys & Dietmar Koenig, Infineon I April 21 | 7:00 a.m. – 7:50 a.m.
Standards such as ISO 26262 define strict requirements, processes, and methods that all stakeholders IP vendors, sub-system and SoC developers must abide by when designing safety critical automotive products. One such requirement is the Development Interface Agreement (DIA) which defines the interactions, interfaces, responsibilities, dependencies and work products to be exchanged between customers, like Infineon, and suppliers for all distributed safety related activities. In this session, we will explain the details of distributed development based on DIA and outline the different activities for which DIAs must be signed during a distributed development process. In the second part of the presentation, Infineon will highlight their approach on meeting SoC-level functional safety objectives while closely collaborating with Synopsys.