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SNUG South Asia 2021 - Proceedings Now Available
Browse over 90 user presentations and tutorials. A SolvNetPlus account is required.
2021 SNUG South Asia Best Presentation Winners
Verification
XLBIST Verification on Netlist Based Emulation
Madhukar Ramegowda, Harshal Kothari, Somasunder Kattepura Sreenath - Samsung
Session Presentation
Verification
Automotive Safety Digital IP Verification and Fault Injection Methodology
Sachin Miglani, Sandeep Arya, Bipin Gupta, Vipin Kumar, Hemant Nautiyal, Amit Rao - NXP Semiconductors
Session Presentation
Verification
ML-RCA and SAM : A Paradigm Shift in CDC Verification
Francis Chockalingam - Broadcom; Amit Goldie, Anup Gupta - Synopsys
Session Presentation
Verification
Verdi RDA: An Automated Regression Debug Solution for Higher Verification Productivity
Han Ying Lim, Wee Chea Chang - MediaTek
Session Presentation
Test
A Novel Approach To Synopsys SMS based In System SRAM Repair Verification in Embedded SoC to Bridge Gap between Test and Functional Mode
H. Kothari, B.V. Madhu, E. Ben Jacob, A.V. Krishna, S.K. Sounderrajan,
S.K. Sreenath - Samsung
Implementation
Pushing Performance of High-performance Compute Cores on Advanced Node of 7nm Using Next Generation Implementation and Signoff Tool
Vikas Singal, Akshay Rai, Mansi Masrani, Muralimanohar Vepadharmalingam - Intel
Session Presentation
Implementation
Enabling Faster Design Closure with Fusion Compiler and PrimeECO
Raghavendra Swami Sadhu, Tamal Sinha, Vishal Jain - Samsung
Session Presentation
Digital Design
RFSoC DFE Block I/O Optimization
John McGrath, Padraig Golden, Paul Ang, Ryan Kinnerk - Xilinx
Session Presentation
Custom Physical Verification
Driving to Entitlement Yield in Foundry and TI Fabs with Synopsys Yield Explorer
David Francis, John F. West -
Texas Instruments
AMS
Memory Yield Estimation Flow using PrimeSim HSPICE AVA and PrimeSim XA
Ashish Kumar - STMicroelectronics; Shubham Varshney -
Zia Semiconductors;
Rakesh Shenoy - Synopsys
Signoff
Estimation of Partition Level External Timing Through Top-Down Constraints Extraction from Full Chip Timing
Wen Sen Tan, Muhammad Hamdi Badrulhisham, Kok Shong Choo - Intel
Session Presentation
Signoff
Voltage Slack and MHz/mV Optimization for Better Chip Power and Performance
Parimal Das, Apurva Chaure, Sanjeev Srivastava - Intel
Session Presentation
Characterization & Transistor
Using ESP-CV for Standard Cell Library Functional Verification
Rajnish Garg, Anuradha Ray, Rohit Goel - STMicroelectronics;
Rakesh Shenoy, Moninder Singh - Synopsys
Systems & IP
Optimizing SoC Simulation Time by >5X Using Instruction Accurate Behavioral Model of ARC
Ravi Mangal, Alagendran Chidambaram - Micron
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