SNUG India - NCR (National Capital Region) Call for Papers

Share your experience using Synopsys tools and IP at the 2019 Synopsys Users Group (SNUG) in India (NCR – National Capital Region, Noida). SNUG brings together Synopsys users, technologists and industry experts for your local technical conference devoted to the challenges of electronic design and verification.

As a published SNUG author, you will increase your visibility in the local design and worldwide Synopsys User communities. In addition to the professional recognition, you will be eligible for significant cash awards (please check your company’s gift acceptance policy).

The call for papers is closed. The SNUG Technical Committee will review the submitted proposals and notify authors about abstract acceptance by March 8, 2019.

We have a preliminary list of topics to get you started, but don't let that limit your ideas or innovation in your submission:

AI and Machine Learning

• Improving Productivity and Achieving Faster QoR Closure with Machine Learning
• Using AI-ready IP to Meet Processing, Memory, and Connectivity Requirements for Deep Learning Applications

Automotive

• Implementing Safety Critical Designs for Automotive Applications
• High Reliability Design Techniques for Automotive Designs

Design PPA, TTR Optimization

• Optimal Design Flow for Digital Implementation of Advanced Node Designs
• How to Achieve Best Performance, Power and Area for Arm, Graphics/GPUs, Processors
• Optimization Techniques for Low-power Designs
• Advanced Design Methodologies

Design Closure and Signoff

• Accelerating Design Closure using Synopsys Fusion Technologies
• Innovative Signoff Methodologies using Synopsys Signoff Tools
• Static and Formal Verification, DRC/LVS, STA, Extraction

FPGA Design & Verification

• Accelerate FPGA Design and Validation Utilizing the FPGA Platform
• Optimizing FPGA Design for Best Area and Performance 

Full Custom Design and AMS Simulation Methodologies

• Productivity Gain from using Custom Compiler
• Productivity Gain from using Custom Compiler In-Design Assistants (DRD, EM/IR, RCx)
• Best Practices in Mixed-signal Verification with Advanced Digital Verification Methodology
• Characterization (Standard Cell, Memory, I/Os, Complex Cells)

Prototyping (Virtual Prototyping, Hybrid Prototyping)

Silicon Test and Yield Analysis

• Highly Efficient, Innovative, Integrated DFT Solutions for Automotive, IOT and Networking Technologies
• Self-testing Techniques for Logic and Memory Testing
• Achieving Lower Pattern Count/Test Time, Faster and Volume Diagnostics using Synopsys Test Solution

SoC Verification

• Best Practices for Estimation and Verification of Low Power Designs
• Verification of System Performance on a SoC or Subsystem
• Best Practices for Verification Coverage Planning and Closure
• Best Practices for Implementing Verification IP (VIP)
• Verification of System Performance on a SoC or Subsystem with Fast Emulation

Successful IP Integration into SoCs

• Interface IP such as USB, PCI Express, DDR, MIPI, Ethernet, Multi-Protocol SerDes, etc.
• Embedded ARC Processors & Embedded Vision Processors
• Integration of IP into Cloud Computing SoC Designs

Software Bring-up

• Accelerating Software Bring-up with Emulation and Prototyping
• Improving Software-driven Hardware Verification with Hybrid-emulation
• Using FPGA-based Prototyping to Accelerate System Validation of IP and SoCs
• Accelerating Software Development with Virtual Prototyping