FPGA Platform Design & Verification Seminar Series 2019

Attendees of this seminar will learn about the Synopsys FPGA Platform to help find and fix bugs faster. The FPGA Platform provides an end-to-end flow, combining accelerated simulation and debug, clock domain crossing, RTL analysis, and the highest performance synthesis.

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Click on location below.

Irvine, CA                                 Registration Closed

Columbia, MD                         May 29

Mountain View, CA                Registration Closed

Marlborough, MA          June 11

Atlanta, GA                     June 19

Huntsville, AL                June 20

Schaumburg, IL             June 26

Contact us if you'd like to schedule a seminar in a city not listed.

Agenda Topics

10:00 a.m - 03:30 p.m.
(Lunch provided)

  • FPGA Platform overview - Find and fix bugs faster!
  • Simulation, debug and the benefits of UVM adoption
  • Clock domain crossing and linting overview
  • Synthesis and design challenges for high reliability
  • Guest speaker - Discussing FPGAs
  • Demonstration of the Synopsys FPGA Platform in action

*Agenda subject to change