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IP
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Overview
Intel and Synopsys set out to address the growing complexity of silicon observability and learning in advanced process nodes and establish a comprehensive Silicon Lifecycle Management (SLM) solution. The goal was to enhance silicon observability and learning by creating an open, automated platform that integrates sensors and monitors from multiple sources, streamlining data analytics and enabling actionable insights across the silicon lifecycle.
Challenges
With increasing complexity in silicon design and validation, Intel needed a robust solution to unify different monitors from Synopsys, Intel, and third-party providers. Automating the flow from sensor integration to silicon data analytics within the Intel product engineering environment was essential to accelerate learning and ensure high-quality results.
Solution
Intel and Synopsys formed a strong, multidisciplinary team spanning chip-level architecture specification, design implementation, pre-silicon validation, test chip tape-out, post-silicon bring-up, and data analytics. Working in close alignment across technical and management stakeholders, the teams built an open platform capable of automated integration of Synopsys SLM monitors and Intel’s proprietary sensors. This solution fully leveraged Intel’s post-silicon framework and Synopsys Silicon.da analytics platform to deliver actionable silicon insights.
Outcome
The partnership resulted in the successful tape-out of the Sensor evaluation PLatform (SePL) test chip on Intel’s advanced 3nm process, with fully automated integration of monitoring IP. The teams achieved targeted KPIs for silicon results using Synopsys SLM monitors and Silicon.da analytics, enabling:
- Process speed comparisons across VT devices (ULVT, LVT, SVT, and HVT) via Synopsys ring oscillators
- Post- to pre-silicon correlation for each device type with Silicon.da Monitor Analytics
- Critical clock frequency measurement using CDM IP
- Functional path margin measurement with PMM IP
- Silicon-based learning of voltage and temperature sensitivity for functional paths
- Identification of timing anomalies and performance outliers via post- to pre-silicon correlation
- HTOL-based aging prediction and Vmin adjustment forecasting for AVS
Benefits
- Silicon proven and validated by Intel, with customizable flows, such as advanced path selection strategies for PMM, to address diverse design objectives
- Synopsys SLM IP integration is fully enabled within Intel’s product engineering workflows, featuring automated processes at both pre-silicon and post-silicon stages for streamlined deployment across Intel groups
- Synopsys’ robust Silicon.da analytics platform provides comprehensive, unified data aggregation and analysis from both Intel and Synopsys IPs, with off-chip data standardization across sensors and monitors enabled by the Unified Data Format (UDF)
