- Silicon Design & Verification
- Products
- Solutions
- Resources
- Services
- Community
- Training
- Silicon IP
- Products
- Markets
- Newsletter
- Customer Success
- News
- Resources
- Company
- About Us
- Investor Relations
- Community
- Newsroom
- Resources
- Careers
DesignWare True Random Number Generator for NIST SP 800-90c
The security strength of many systems and applications is dependent on the quality of random number generators. Many cryptographic operations require a source of random numbers, such as the creation of cipher keys and initial values for counters and protocol parameters.
The DesignWare® True Random Number Generator (TRNG) Core for NIST SP 800-90c is compliant with NIST SPA800-90A/B/c and BSI AIS 20/31 specifications. It generates random numbers that are statistically equivalent to a uniformly distributed data stream. The core includes a NIST SP800-90B approved conditioning circuit with a compliant noise source and NIST SP 800-90A approved Deterministic Random Bit Generator (DRBG) using the terminology preferred by the National Institute of Standards and Technology (NIST). The core generates random numbers that are intended to be statistically equivalent to a uniformly distributed data stream. The noise source does not depend on process-specific circuitry and is therefore very portable across different ASIC and FPGA fabrication technologies. When implemented in silicon, the DesignWare TRNG can meet or exceed the highest commercial and US government SBU standards.
DesignWare True Random Number Generator Core for NIST 800-90c
- NIST “Live, Enhanced NRBG”
- Compliant with NIST SP800-90A/B/c, AIS 20/31, FIPS 140-2 and FIPS 140-3
- Designed for compliance with OSCCA certification
- Customer configurable
- Wide system clock dynamic range
- Virtualization support (up to 8 TRNGs)
- Selectable number of seed generators: 6 or 8
- Background raw noise collection for fast reseeding
- Redundant internal seed generators
- Continuous statistical and on demand known answer health tests
- Serial output stream for auxiliary uses (differential power analysis and timing analysis)
- Various interfaces supported: memory mapped (AXI/AHB/APB), serial random bit streams (up to 3), and nonce interface compatible with DesignWare HDCP Content Protection ESMs