Join this webinar to learn more about the joint efforts of IBM Research and Synopsys and recently developed Atomic-Scale QuantumATK to TCAD Raphael FX Workflow on supporting the exploration and eventual integration of alternative metals in advanced logic interconnect technology. This work is part of the IBM Research and Synopsys collaboration on accelerating post-FinFET process development with Design Technology Co-Optimization (DTCO) innovations.
- Scaling of logic technologies to the 3nm node and beyond, motivates the evaluation of new metals for the power rails and signal wires. The purpose is to mitigate the rising impact of interconnect parasitics on performance.
- The current solution which is based on copper and a barrier metal shows a significant rise in resistivity as conductor widths decrease, and eventually leads to lower performance and higher IR drop.
Participate and gain insights on:
- How to simulate vertical resistance in vias, i.e., interfaces between various conductor, adhesion liners, wetting, and diffusion layers.
- How to efficiently evaluate resistance due to scattering at grain boundaries (GBs) in metals by using Sentaurus Materials Workbench (SMW) under QuantumATK.
- SMW automates key tasks including easily building and relaxing a large set of GBs, calculating GB reflection coefficients, and GB resistivity for different average grain sizes.
- How the results from SMW can be automatically incorporated into the TCAD Raphael FX simulations
- For handling extraction of interconnect resistance and capacitance of complex process structures.
Audience with atomic-scale, TCAD, and technology development experiences, especially in working with advanced logic processes, will greatly benefit by attending.
You are welcome to ask questions throughout the webinar or at the end during the Q&A session.