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The Synopsys DesignWare® USB 1.1 Host Controller (OHCI) IP is USB IP Host core that ASIC/FPGA designers can use to implement a complete USB OHCI Host controller. The Host runs at USB Full and Low Speeds. Nearly all commercial, open source, and real-time operating systems support the OHCI standard out-of-the-box. This speeds development time saving years of engineering effort. By utilizing Synopsys' production-proven USB IP, designers can significantly reduce development time and engineering risk, and bring their USB-based solutions to market faster. DesignWare USB 1.1 Controller IP Datasheet
- Low gate count and low power consumption
- Mature, silicon proven, shipped in billions of units
- AHB enables rapid integration in SoCs
- Save engineering effort: Compatible with the Open HCI (OHCI) specification, with broadly available drivers. Nearly all operating systems have OHCI Host software stack support built in.
- Available in Verilog
- Configurable root hub supporting multiple downstream ports
- Configuration data stored in Port Configurable Block
- 12MHz and 48MHz input clock
- Integrated DPLL
- Support for SMI interrupts
- Low gate count, starting at 30k gates
- Test environment includes integration tests
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