Synopsys Multi-Protocol 112G PHY IP

Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high performance multi-rate transceiver portfolio for high-end networking and high performance computing applications. The area-efficient PHY provides a low active and standby power solution that supports multiple electrical standards, including PCI Express® (PCIe®) 6.0, 1G to 112Gbps electrical PHY for 400G/800G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), Compute Express Link (CXL), JESD204C, CPRI, SATA, and other industry-standard interconnect protocols. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 112GG PHY delivers signal integrity and jitter performance that exceeds the standards electrical specifications.

The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations. The multi-protocol 112G PHY provides advanced power management features for both standby and active power. The BERT and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Coding Sublayer (PCS) and Media Access Control (MAC) for 200G/400G/800G links to deliver a complete solution, reduce design time and help designers achieve first-pass silicon success.

Synopsys Multi-Protocol 112G PHY IP Datasheet

DesignCon 2021: 112G Ethernet & PCIe 6.0 IP Performance & Interoperability Demos | Synopsys

This video features Synopsys silicon-proven DesignWare 112G Ethernet and PCIe 6.0 PHY IP solutions successfully interoperating with Samtecs AI/ML edge connectors and Amphenols Direct Attach Copper (DAC) cables with superior Bit Error Rates (BERs) at maximum performance.

 

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  • Supports 1.25 to 112 Gbps data-rate
  • Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols
  • Supports x1 to x16 macro configurations with aggregation and bifurcation
  • Spread Spectrum Clock (SSC) support for PCIe
  • PCIe Separate Refclk Independent SSC (SRIS) and power management features
  • Ethernet Electrical Energy Efficient (EEE)
  • Reference clock sharing for aggregated macro configurations
  • ADC/DSP based PVT invariant architecture
  • Embedded bit error rate tester (BERT) and internal eye monitor
  • Supports IEEE 1149.6 AC Boundary Scan
112G LRM PHY, TSMC N5 x2, North/South (vertical) poly orientationSTARs Subscribe
112G PHY, TSMC N3P x4 1.2V, North/South (vertical) poly orientationSTARs Subscribe
112G PHY, TSMC N5 x2, North/South (vertical) poly orientationSTARs Subscribe

Description: 112G LRM PHY, TSMC N5 x2, North/South (vertical) poly orientation
Name: dwc_112g_lrm_phy_tsmc5ff_x2ns
ECCN:
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: Contact Us for More Information
  
Description: 112G PHY, TSMC N3P x4 1.2V, North/South (vertical) poly orientation
Name: dwc_112g_phy_tsmc3pff12_x4ns
ECCN: 5E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation: Contact Us for More Information
Product Code: G645-0
  
Description: 112G PHY, TSMC N5 x2, North/South (vertical) poly orientation
Name: dwc_112g_phy_tsmc5ff_x2ns
Version: 3.07a
ECCN: 5E991/NLR
STARs: Open and/or Closed STARs
myDesignWare: Subscribe for Notifications
Product Type: DesignWare Cores
Documentation:
Download: dwc_112g_phy_tsmc5ff_x2ns
Product Code: H733-0