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DesignWare DDR2/DDR SDRAM Memory Controller

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The Synopsys DesignWare® DDR2/DDR SDRAM Memory Controller IP (MCTL) offers an efficient digital interface between up to 32 on-chip application buses and a DDR2/DDR physical layer (PHY) in a DDR2 or DDR memory subsystem. The MCTL IP is a full-featured controller that provides efficient DDR control and protocol translation, support for multiple application ports, quality of service (QoS) control and optimized memory transaction scheduling. The MCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data training.

DesignWare DDR Complete Solution Datasheet
 

  • Provides a complete, single vendor DDR2/DDR SDRAM interface solution, when combined with the DesignWare DDR2/DDR PHY IP
  • Supports JEDEC-standard DDR2 and DDR protocols (JESD79-2 and JESD79, respectively)
  • Supports data rates of up to 1066 Mbps (533 MHz)
  • Includes a configurable multi-port arbiter with up to 32 host ports using Host Memory Interface (HMI) or AMBA 3 AXI
    • Programmable ultra-high priority port (port 0), typically a CPU port
  • Separate configuration port using Controller Register Interface (CRI) or AMBA 3 AXI with independent clocking
  • Command re-ordering and scheduling to maximize memory bus utilization
    • Command reordering between banks based on bank status
    • Programmable priority arbitration and anti-starvation mechanisms
    • Configurable per-command priority with up to eight priority levels; also serves as a per-port priority
  • Automatic scheduling of activate and precharge commands
  • Automatic scheduling of refreshes
  • Supports memory interfaces of 8 to 64 bits in 8 bit increments (up to 72 bits with ECC)
  • Programmable ECC generation, checking, and correction
  • Support for up to four external memory ranks
  • Contains basic data training logic for supporting DesignWare DDR2/DDR PHYs
  • Automated Read DQS recognition with Dynamic Drift Compensation
  • Programmable timing parameters support DDR2/gDDR2/DDR/gDDR SDRAM components from various vendors