DesignWare System-Level Library Release Adds 20 New Titles, Plus Model Authoring Kits

Synopsys announces the latest release of the DesignWare® System-Level Library, Synopsys' portfolio of abstract models that serve as the building blocks for virtual platforms. We have added more than 20 titles, most notably transaction-level models (TLMs) for:

• PowerPC 405, 440 and 460 cores
• DesignWare USB 2.0 Host Controller and SATA Host Controller, which join the TLMs of other DesignWare Cores such as USB 2.0 HS OTG, PCIe, SATA Advanced Host Controller, and GMAC already in the System-Level Library
• ARM PrimeCells, including DMAC, Interrupt Controller, UART, dual timer, watchdog, and inter-processor control

These TLMs represent a programmer's view or loosely timed (LT) following the new OSCI TLM-2.0 nomenclature. The System-Level Library is delivered with dedicated virtual platform examples that can be used as references or as starting point for a customer-specific virtual platform.

MAKe your own transaction-level model
In addition to the 100 ready-to-use models, this new release of the DesignWare System-Level Library introduces Model Authoring Kits (MAK) for UART, USB EHCI and USB Host. You may find a need to build your own transaction-level model, matching your particular RTL IP configuration. In the past you had to rebuild this TLM from scratch. However, there are many common elements in any set of configurations for a given piece of IP, and these common elements are modeled in our MAK, provided as C++ classes. These classes can be used to quickly assemble a TLM model of your particular RTL implementation configuration. To create a TLM for a unique IP configuration (e.g., extra registers for PHY control), you now only need to develop the portion of the model specific to your additional component(s), significantly reducing your development effort.

All new titles and MAK's are available immediately to licensees of the DesignWare System-Level Library, at no additional cost.