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The "Low Power Methodology Manual" (LPMM) is a comprehensive and practical guide to managing power in system-on-chip designs, critical to designers using 90-nanometer and below technology.
The authors, all low power experts, are led by Michael Keating, Synopsys Fellow and principal author of the widely adopted Reuse Methodology Manual for System-on-Chip Design, and David Flynn, ARM R&D Fellow and original architect behind ARM's synthesizable CPU family and the AMBA® on-chip interconnect standard.
Combining extensive commercial experience, deep scientific understanding, silicon technology case studies, and a pragmatic approach, the authors describe design techniques which address both dynamic and static (leakage) power, including methods for power gating and dynamic voltage and frequency scaling. For each topic, the authors describe the design challenge, provide a technology foundation, and then make specific recommendations as well as a caution against design pitfalls. This book is a must-read for anyone designing, or getting ready to design, SoCs for low power applications.
Synopsys customers with a valid SolvNet ID and password can download a free PDF copy of the Low Power Methodology Manual.
If you would like a printed copy, you can purchase the Low Power Methodology Manual from Amazon.com, or you can order a copy through any bookstore (ISBN: 978-0387718187).