Fusion Technology Lunch

IC Compiler II Lunch
Breakthrough Fusion Technology with IC Compiler II Enabling Best QoR on Advanced Designs

Monday, June 25, 2018
11:30 a.m. - 1:30 p.m.
Marriott Marquis Hotel
B2 Level, Golden Gate Ballroom
780 Mission St, San Francisco, CA 94103

Paradigm-shifting Synopsys Fusion Technology changes the RTL-to-GDSII design flow with the union of best-in-class optimization and industry-golden signoff tools. Fusion Technology enables designers to accelerate the delivery of next-generation designs using shared engines across the industry’s premier digital design tools and using a unique Fusion data model for both logical and physical representation. Fusion Technology brings Design Compiler Graphical, PrimeTime, StarRC, and RedHawk analysis technologies into the hands of the IC Compiler II user.

Attend this lunch event to hear from leading customers how Synopsys Fusion Technology has redefined conventional EDA tool boundaries across synthesis, place-and-route, and signoff to address advanced-node design challenges and accelerate products to market.

Agenda

11:30 a.m. – 11:45 a.m.  
11:45 a.m. – 12:00 p.m.   
12:00 p.m. – 1:15 p.m.  
1:15 p.m. – 1:30 p.m.

Doors Open/Registration/Complimentary Lunch Served
Welcome and Introductions
Panelist Presentations
Conclusion and Prize Drawing

Register Now!

Attendence at this event is free, but registration is required. Seating is limited, so reserve your seat early.

Exhibit Hours:

Mon: 10:00 a.m.– 6:00 p.m.
Tue: 10:00 a.m.– 6:00 p.m.
Wed: 10:00 a.m.– 6:00 p.m.