|Thursday, September 19, 2019 9:30am - 5:15pm PDT|
|Santa Clara Marriott
2700 Mission College Blvd, Santa Clara, CA 95054
This free one-day event consists of multiple tracks in which Synopsys experts, ecosystem partners and the ARC user community will deliver technical presentations on a range of topics, including, artificial intelligence (AI), machine learning, automotive safety, internet of things (IoT), embedded vision and much, much more.
Come and learn about the latest technologies and trends in embedded processor IP, software, programming tools and applications.
The embARC Machine Learning Inference (MLI) software library is optimized for low-power IoT applications that utilize convolutional neural networks (CNN) and recurrent neural networks (RNN). During this workshop, participants will get hands-on experience using the MLI library on the Synopsys ARC EM processor, by building an application which uses a CNN to recognize hand-written characters.
|9:30 - 10:00am||Check-in and Breakfast||10:00 - 10:15am||Welcome & Opening Remarks||10:15 - 11:15am||Keynote: Designing in the Age of AI
Chekib Akrout, Senior Vice President, Design Group Customer Excellence, Synopsys
|11:15 - 11:30am||Break|
|11:30 - 12:15pm||Implementing an Ultra-low Power Solution for Always-On, Smart Vision Applications - Himax||System Modelling for Real-Time Automotive Applications using Deep Learning and Complex Data Processing - Infineon||Addressing IoT Connectivity Challenges with Low-power NB-IoT Modem Solutions - Palma Ceia SemiDesign|
|12:15 - 1:00pm||Creating Intelligent Facial Landmark Tracking Applications with Synopsys EV Processors - ULSee||ISO 26262 Compliant IP and SEooCs - Getting It Right! - exida||Verifying the Security of ARC Processor-based Systems with Radix-S - Tortuga Logic|
|1:00 - 2:00pm||Lunch|
|2:00– 2:45pm||Leveraging Recurrent Neural Networks (RNNs) to Efficiently Process Sequential Data - Synopsys||Safety First! Driving Functional Safety from the Processor Level for Automotive ADAS Systems - Synopsys||Embedded Multicore Application Development with Zephyr and ARC Processors - Synopsys|
|2:45 – 3:30pm||Using Artificial Intelligence to Harness the Coming Data Explosion - Synopsys||The Future of Functional Safety: AUTOSAR Software with an On Die Safety Island - Elektrobit||Next-Generation Voice and Audio for Wearable Devices with the Low Complexity Communication Codec (LC3) - Fraunhofer IIS & Synopsys|
|3:30 - 3:45pm||Break|
|3:45 - 4:30pm||CNN Graph Optimization and Partitioning for Performance & Latency Improvement - Synopsys||Using MathWorks MATLAB with ARC MetaWare Development Toolkit - Ashling||Enabling Ultra-High Performance, Low-Power 5G Modem Designs with Heterogeneous Multicore Systems - Synopsys|
|4:30 - 5:15pm||Applying New Vision and Deep Learning Trends to Edge Applications - Synopsys||Advanced Vector Floating Point DSP Processing for Automotive Applications - Synopsys||Speed, Accuracy, Performance, and Visibility - ARC Processor Simulation without Compromise! - Synopsys||5:15 - 6:30pm||Networking Reception & Demos|
Few technologies over the past 50 years have had the potential for disruptive change in our society as artificial intelligence (AI). With technology industry giants and startups alike focused on bringing the capabilities of machine learning into a broad range of devices from the cloud to the edge, the race is on. This keynote will discuss the drivers for implementing AI across a broad range of chip architectures and technologies that are being embraced by leading design teams to accelerate the integration of AI into their SoCs.
The need for intelligent computer vision solutions is increasing in the emerging market for edge devices. The Himax WiseEye 2.0 intelligent vision solution, leveraging a proprietary ARC processor-based ASIC, specializes in processing AI-based algorithms for ultra-low power, “always-on” image sensing. The ASIC’s advanced features enable inclusion of intelligent optical recognition in smart homes, smart buildings, security cameras, smart cars, and consumer IoT devices. WiseEye 2.0 is one of the most efficient intelligent vision solutions on the market, using less power and computing resources.
Real-time, dynamic face tracking is key for virtual try-on, augmented reality, and driver safety applications. In this presentation, we will describe applications that use facial landmark tracking. We will discuss some critical challenges that we addressed to account for lighting, clothing, and other variables for deployments to Volkswagen, UNIQLO, Disney, and more. We will explain how the MetaWare EV toolchain and Synopsys EV Processors help accelerate the development of SoCs for advanced driver assistance systems (ADAS), driver monitoring systems (DMS), and visual try-on applications.
Machine learning utilizing neural networks has improved task solving in multiple application domains. Convolutional neural networks (CNNs) revolutionized image processing algorithms, however, the use of CNNs for non-visual data sets has had more limited success. More state-aware processing is required for sequential data such as acoustical signals, natural language, and accelerometer-based gestures. Recurrent neural network (RNN) architectures such as Long Short-Term Memory (LSTM) leverage previous state (feedback) to determine the current state of the network. RNNs are algorithmically more complex and offer higher variability in terms of network topologies and building blocks, limiting usefulness of hardwired general purpose RNN engines. Programmable processing cores enable future-proofing as next generation neural networks are developed. Optimal implementation of RNN cells on a power efficient processor can provide outstanding performance and energy savings critical for deeply embedded solutions.
We are in the midst of a data explosion. Autonomous vehicles, augmented reality, machine vision, the internet and augmented reality are all increasing rapidly in capability. The common link in these capabilities is the large amounts of data that they generate. Most of the data is being created outside of the data center and transporting data from where it resides to the core or cloud for processing is becoming challenging. As data grows Artificial Intelligence will be used to manage it focusing on where data is stored, when it is moved and where it is processed. Offline processing will also increase, and AI can be used to process the data and then move it later to the cloud as needed. This presentation will look at the challenges that we face with data and how artificial intelligence can be used to overcome them.
There is often a demand to maximize inference performance on a given system. This presentation will introduce optimization and partitioning techniques designers can use with the Synopsys EV Processor to improve design metrics, including performance, bandwidth and latency. We will discuss various optimization techniques such as quantization, graph compression, and co-efficient pruning of CNN graphs and how to partition the graphs over the DNN Engine to improve performance and latency.
Embedding computer vision and deep learning at the edge remains challenging today because of the huge computational and memory requirements and due to the pace of innovation of algorithms for modern vision and sensing tasks. CNN graphs particularly are rapidly evolving to improve the accuracy and speed of learning and inference. Mapping these vision and deep learning algorithms on low power embedded platforms are demanding on computational complexity, bandwidth and accuracy. In this presentation, we will discuss the latest computer vision trends and deep learning techniques for embedded platforms and how these trends are shaping the latest enhancements to the Synopsys EV Embedded Vision Processor IP family.
Innovation in the automotive industry is defined by autonomous driving and reduction of CO2 emissions. For the next 15 years, the industry will develop cars with combustion engines, battery electrical vehicles and hybrid cars. To minimize CO2 emissions globally for the mix of these different powertrain architectures, predictive system control strategies have to be used. For this purpose, the characteristic of the powertrain architecture has to be described with corresponding system models. Several mechanical and thermomechanical elements of the powertrain are not representable by linear differential equations. Artificial Neural Networks (ANNs) and stochastic algorithms like particle filters are methods to get mathematical models for such non-linear elements. Kalman Filters and ANNs are used for the predictive based system control approaches. The topology of these algorithms use matrix-vector operations and vector-vector operations together with non-linear mathematical base functions. To fulfill the performance requirements for a real-time automotive application like powertrain, these algorithms has to be executed on a powerful VDSP architecture like Synopsys’ ARC EV processors.
Automotive safety IPs and SEooCs are offered left and right! “ASIL-D with Certification” – Product announcements and press releases promise it all. However, users soon realize how much work is left to be done and that certified components are often not as magical as advertised.
This presentation gives a clear overview and guidance, how ISO 26262 compliant IP and SEooC must be specified and designed, and which additional safety collateral and information must be provided to enable proper integration. Users are advised what to ask for, what to accept or reject, and how to work around some typical shortcomings of their suppliers.
Drivers are the biggest uncertainty factor in cars, and advanced driver assistance systems (ADAS) are helping to mitigate human error and make the roads safer. Designing SoCs for ADAS applications, including lane departure warning, adaptive cruise control, and autonomous vehicles that can ‘see’ in fog, heavy rain, pitch darkness, and air pollution, requires ASIL Ready processor IP. In this presentation, we will describe the challenges of designing functionally safe processor IP that can meet the highest safety levels, up to ASIL D, for high-performance in-vehicle processing.
Increasing system complexity is challenging conventional safety techniques and requiring automakers to provide customers with vehicles that can be updated with the evolution of software. This can be both expensive and time consuming. However, integrating the safety island on the SoC permits unique system connections to the different functional blocks enabling safety management through classic and adaptive AUTOSAR. Using a combined hardware and software solution for the safety concept provides a best-cost solution while meeting dynamically evolving safety requirements throughout a vehicle’s lifecycle.
MathWorks MATLAB/SIMULINK is a mathematical programming platform allowing the development of algorithms, data analysis, and the creation of models and applications. The MetaWare MATLAB/SIMULINK plugin integrates the Synopsys MetaWare Development Toolkit into MATLAB/SIMULINK, allowing compilation of generated ‘C’ language models and applications into highly-optimized code tuned for running on Synopsys ARC targets. This presentation will provide an overview of how the plug-in works and demonstrates its usage with MATLAB designs.
Automotive applications such as Advanced Driving Assist Systems (ADAS), engine management, and powertrain require increasing levels of complexity as well as high levels of precision and accuracy in terms of algorithms and data formats. As algorithm complexity grows, system architects are developing their algorithms with tools such as MATLAB, which work in high-precision data formats such as half and single precision floating point.
These large amounts of computation need a specific core for large vector floating point DSP. The EV6x processor has three dedicated vector floating point computation pipes that gives industry-leading levels of throughput, as well as hardware acceleration for linear algebra mathematical functions.
Low power IoT connectivity requires modem chipsets and integrated wireless options to enable cost-effective deployment. Narrow-band IoT (NB-IoT) is a key 3GPP cellular communication standard that makes this possible. This talk will cover the aspects of the NB-IoT protocol that make it a “go-to” technology for IoT and will highlight how both Palma Ceia SemiDesign and Synopsys applied their respective IP to provide a complete NB-IoT solution, shortening the time-to-market for developing IoT communication products such as multimode edge-based IoT devices or stand-alone chipsets.
Security is a first-order design requirement for processor-based systems. Processor designers implement security functionality directly into the hardware itself to protect the system at its most fundamental layer. System integrators that use processor IP such as Synopsys ARC® processors must ensure that they configure and manage the protection and security features correctly, and that they do not introduce vulnerabilities.
Evaluating the security levels and vulnerabilities of complex, highly combined hardware-software systems is hard. In this talk, we outline a general methodology for combined hardware-software security verification for ARC-based platforms using Tortuga Logic’s Radix-S software. We demonstrate how Radix-S can be used to detect security vulnerabilities resulting from misconfiguration of hardware security features by creating an example system comprised of the ARC processor and vulnerable software that configures the memory protection unit incorrectly. With Radix-S, we quickly identify the flaw using standard functional verification techniques. Furthermore, we show how system integrators can verify the security of secure debug logic with this technology.
Performance in Desktop, Server and HPC applications has been scaling rapidly in recent years via multicore, continuously increasing the number of cores on a processor chip. The same principle has been extending to embedded systems, where multicore designs are increasingly more pervasive in embedded applications such as 5G data processor, edge IoT machine learning and many more.
This presentation will examine multicore application options and considerations using the Zephyr RTOS. We will introduce the Zephyr RTOS, its main features and multicore support models (AMP and SMP). We will discuss challenges associated with designing high-performance software applications for multicore and contrast AMP and SMP approaches using samples applications on modern ARC processors.
Wearable wireless audio devices are fast becoming the next battle ground in terms of consumer product focus and differentiation. These look to offer voice and audio streaming via wireless protocols like the Bluetooth communication standard whilst combining function with fashion – a trend expected to rise with the further emergence of wireless networks.
Bluetooth is going to adopt the Low Complexity Communication Codec (LC3) for upcoming LE profiles. It solves the problem of poor audio quality for voice and audio over Bluetooth link to enable quality similar to wired connection. Previously used codecs originate from last century, so it has become high time to introduce state of the art codec knowledge. The superior audio quality of LC3 is achieved at reduced data rates to support the needs of ultra-low power wearable devices.
Furthermore, the Low Complexity Communication Codec Plus (LC3plus), which is currently under standardization in ETSI, brings the high-quality super-wideband-voice user experience to devices using the DECT and VoIP link and doubles the capacity for wideband audio. With an extended dynamic range, a high signal-to-noise ratio, as well as a low total harmonic distortion, the LC3plus high-resolution mode makes the codec suitable for transmitting high-resolution audio content and enables new applications in DECT.
The LC3 codec has been ported and optimized to the Synopsys ARC EM and HS processors, which offer high performance and ultra-low power, ideally suited for battery-operated wearable devices.
The ITU 5G standard pushes the requirements on wireless communication equipment for greater than 1Gbps data rates with reduced system latency, allowing an expansion of 5G use cases to automotive and other timing-critical IoT applications. SoC modem developers for 4G systems previously met performance requirements with heterogeneous systems, using multiple task-specific processor cores.
User Equipment (mobile devices) 5G modem SoCs will need to take the heterogeneous implementation further to provide greater computation for higher data rates, larger MIMO configurations, and lower latency, while maintaining similar power budgets to 4G modems. This session will go through the range of digital signal processors, controller cores, task-specific cores, and system connection schemes that will allow 5G mobile modem SoC developers to implement the required amount of programmability/flexibility in their design, while achieving the performance and low-power requirements.
Instruction set simulators (ISS) are vital for compiler, operating system, and application development, as well as processor architecture design space exploration and verification. Because the demands for each are so different, designing an ISS that caters to all of the above application scenarios is a constant challenge. In this session we first want to show the versatility of the Synopsys ARC nSIM simulator by demonstrating how it addresses all of the above requirements. Finally, we will highlight the latest feature of nSIM, its high-speed cycle-approximate simulation mode (NCAM). We will show key NCAM use-cases such as how to arrive at the best hardware configuration, derive the best compiler optimizations, and have a fully optimized application much before final silicon is available.
Real-Time Trace for ARC Processors – Ashling Ultra-XD Hardware Trace Probe – Ashling
The Ultra-XD Trace Probe allows you to capture trace from an ARC HS or EM core and upload it to the MetaWare Debugger at gigabit Ethernet speeds. Captured trace can be turned into a “replay” database enabling you to debug your program by executing it both forwards and backwards. Developed in cooperation with Synopsys, the Ultra-XD probe integrates with the MetaWare or GNU GDB Debuggers under Windows or Linux based hosts.
Debugging ARC with Lauterbach TRACE32 – Lauterbach
Lauterbach will demonstrate debugging on an ARC EM processor target using the TRACE32 debugger including source level code debugging with full on-chip breakpoint support such as program breakpoints, address read/write breakpoints, data breakpoints for memory writes and breakpoints on auxiliary registers.
Tracealyzer for OpenVX and Device Firmware Monitor – Percepio
Percepio Tracealyzer for OpenVX allows you to visualize the execution of OpenVX applications and identify bottlenecks where optimization can make a big difference. Tracealyzer for OpenVX is initially available for Synopsys EV6x embedded vision processors, leveraging the built-in trace support in Synopsys ARC® MetaWare EV Development Toolkit.
Percepio Device Firmware Monitor (DFM), is a ground-breaking new cloud service for IoT product organizations that provides awareness of firmware problems in deployed devices and speeds up resolution. When a firmware issue has been detected, DFM notifies the developers within seconds and provides diagnostic information about the issue, including a trace for Percepio Tracealyzer. This shows what was going on in the code when the error occurred, making it far easier to understand the problem and quickly find a solution.
Fast, Quantum Resistant Authentication and Data Protection for the Synopsys ARC – SecureRF
This demo features SecureRF’s “WalnutDSA” digital signature verification method plus “Ironwood” key agreement protocol running in software-only on the ARC IoT SoC. These cryptographic primitives enable ARC developers to implement critical security functions such as secure boot, secure firmware update, remote device authentication, data integrity, data confidentiality, and more. Because of the methods’ high performance in software-only is production-ready, developers can incorporate them into existing designs. SecureRF’s methods are coded in ARC assembly language for speed optimization. The methods are also available with ARC APEX acceleration for the most performance-critical applications.
The demo highlights SecureRF’s performance advantage by comparing the runtime of its methods with equivalent Elliptic Curve Cryptography (ECC) methods: “ECDSA” and “ECDH”. The demo consists of two ARC IoTDK boards and a notebook PC. One IoTDK board is programmed to perform SecureRF’s signature verification and shared secret computation in a loop as fast it can. The other board is programmed to do the same for ECDSA and ECDH. At the conclusion of each signature verification/shared secret computation, each board sends a single character to the PC (“S” for SecureRF, “E” for ECC). Upon receiving the character, the PC draws a single horizontal line of pixels on its display. The lines of pixels form an image of a padlock, the padlock paints on-screen at a rate proportional to the speed of signature verifications/shared secret computations.
Verifying the Security of ARC Processor-based Systems with Radix-S – Tortuga Logic
In this demo, Tortuga Logic will demonstrate how Radix-S can be used to detect security vulnerabilities resulting from misconfiguration of hardware security features in ARC Processor-based systems. With Radix-S, we quickly identify the flaw using standard functional verification techniques. Furthermore, we show how system integrators can verify the security of secure debug logic with this technology.
The Real-Time Robust Facial Landmark Tracker on Synopsys EV62 – ULSee
Real-time, dynamic face tracking is key for virtual try-on, augmented reality, and driver safety applications. In this demo, we show the robust facial landmark tracker by using Synopsys EV62 processor. Currently, the presented hardware device is considered as a deep-learning accelerator to connect to the laptop for POC purpose, and we will release the stand-alone device in the coming future. Experimental result shows that we achieve real-time requirement when performing our facial landmark tracker model by using Synopsys EV62 processor.
Low-Power NB-IoT Communications – Synopsys
Come see a demonstration of our low-power NB-IoT communications solution integrating Synopsys’ ultra-efficient ARC EM9D processor, software stacks and a fully-adaptable, multi-band LTE Cat NB1/NB2 RF transceiver. Leveraging an Amarisoft eNodeB, you can see this solution provide real-world SMS communications between a mobile phone and the Synopsys NB-IoT UE.
Synopsys ARC EV6x Embedded Vision Processors for Safe Automotive SoCs – Synopsys
This demonstration will show the ARC EV6x processors executing drowsiness detection, object detection, and lane detection for safety-critical automotive applications. The Synopsys ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications, combining the flexibility of software solutions with the low cost and low power consumption of hardware. For fast, accurate object detection and recognition, the EV Processors integrate an optional high-performance convolutional neural network (CNN) engine. The EV6x Vision Processor IP with Safety Enhancement Package (SEP) was named "Best Processor" by the Embedded Vision Alliance as part of its annual Vision Products of the Year Award program.
ARC Software Development at Full Speed – Synopsys
The ARC HS Development Kit (HSDK) contains an ASIC implementation of a quad-core ARC HS Processor and a rich set of peripherals including Ethernet, WiFi, Bluetooth, USB, I2C, SPI and UART. It is supported by the tools and software necessary to develop Linux, RTOS and bare-metal applications. Linux distributions can be built for the platform using the open-source Yocto Project and RTOS & bare metal applications can be developed with the embARC Open Software Platform (OSP). This demonstration will show the ARC HSDK in action, showing a great way to get started quickly with software development on ARC processors.
Accelerating Software Development and IP Evaluation with Bluetooth LC3 Codec on Synopsys IP – Synopsys
This demo shows one of the industry’s first LC3 Codec running audio and voice streaming using Synopsys ARC EM Processor IP. The demo is of a complete Synopsys Bluetooth Low Energy PHY and Link Layer IP and Synopsys ARC EM Processor demonstration system for Bluetooth 5 and Bluetooth Mesh capabilities into your IoT SoCs. The complete solution enables SoC designers to jump start their next design with industry proven open source software.
Written Character Recognition using embARC Machine Learning Inferences (MLI) and ARC EM Processors – Synopsys
This demo highlights building a CNN based application to recognize hand-written characters leveraging a Synopsys ARC EM processor and the embARC MLI library. Characters drawn on the screen will be passed to an EMNIST based neural network, which recognizes and displays the character on the screen along with the confidence value.
Advanced EV6x Software Development & Debug with Synopsys Virtualizer – Synopsys
Synopsys will demonstrate the EV6x Virtual Prototype which can be used by EV6x licensees to shift left their software development and improve their debug productivity. The demo will showcase the advanced, non-intrusive HW/SW co-debugging features of the EV6x virtual model, as well as integration with the ARC MetaWare EV debug solution. Moreover, we will demonstrate the customization of this prototype to model your EV6x-based SoC.
Formal Verification of ARC EV and HS Control and Datapath Blocks – Synopsys
Synopsys’ ARC EV and HS processor IP designers use VC Formal to formally verify much of the processors’ complex control and datapath blocks. This demo will show ARC users how to leverage VC Formal and formal methodology to find bugs in their own designs and accelerate verification closure with higher confidence. We will showcase VC Formal Apps with emphasis on FPV and DPV capabilities.
End-to-End Functional Safety Verification for ARC Processors – Synopsys
Synopsys will demonstrate key tools used in the functional safety verification flow to ensure ARC processor-based systems designed for the automotive market meet required standards. The demo will showcase the use of safety analysis to drive the functional safety verification effort. Synopsys functional safety verification tools enable identification of areas that may need hardening as well as running a fault campaign. The demo will also introduce how formal verification and emulation fit into the functional safety verification flow, all while using the same underlying technology to link the various tool results together.