ARC Processor Summit 2019

Your Embedded Edge Starts Here


Join Us at ARC Processor Summit 2019
Thursday, September 19, 2019
9:30am - 5:15pm PDT
Santa Clara Marriott
2700 Mission College Blvd, Santa Clara, CA 95054

This free one-day event consists of multiple tracks in which Synopsys experts, ecosystem partners and the ARC user community will deliver technical presentations on a range of topics, including, artificial intelligence (AI), machine learning, automotive safety, internet of things (IoT), embedded vision and much, much more.

Come and learn about the latest technologies and trends in embedded processor IP, software, programming tools and applications.



Time Description
9:30 - 10:00am Check-in and Breakfast
10:00 - 10:15am Welcome & Opening Remarks
10:15 - 11:15am Keynote Address
11:15 - 11:30am Break
AI/Machine Learning Automotive IoT/Comms
11:30 - 12:15pm Implementing an Ultra-low Power Solution for Always-On, Smart Vision Applications - HiMax System Modelling for Real-Time Automotive Applications using Deep Learning and Complex Data Processing - Infineon Addressing IoT Connectivity Challenges with Low-power NB-IoT Modem Solutions - Palma Ceia SemiDesign
12:15 - 1:00pm Creating Intelligent Facial Landmark Tracking Applications with DesignWare EV Processors - ULSee ISO 26262 Compliant IP and SEooCs - Getting It Right! - exida Verifying the Security of ARC Processor-based Systems with Radix-S - Tortuga Logic
1:00 - 2:00pm Lunch
2:00– 2:45pm Welcome to the Machine Age – Low-Power Machine Learning Inference for IoT - Synopsys Safety First! Developing 4D High-Resolution Imaging Radar SoCs for Autonomous Vehicles - Arbe Robotics Embedded Multicore Application Development with Zephyr and ARC Processors - Synopsys
2:45 – 3:30pm Using Artificial Intelligence to Harness the Coming Data Explosion - Synopsys Using MathWorks MATLAB with ARC MetaWare Development Toolkit - Ashling Enabling Ultra-High Performance, Low-Power 5G Modem Designs with Heterogeneous Multicore Systems - Synopsys
3:30 - 3:45pm Break
3:45 - 4:30pm Partitioning Graphs Across Multiple CNN Engines for Performance & Latency Improvement - Synopsys Developing for Automotive with AUTOSAR on ARC Processors - Elektrobit Speed, Accuracy, Performance, and Visibility - ARC Processor Simulation without Compromise! - Synopsys
4:30 - 5:15pm Applying New Vision and Deep Learning Trends to Edge Applications - Synopsys Advanced Vector Floating Point DSP Processing for Automotive Applications - Synopsys Next-Generation Voice and Audio Streaming Technology for Wearable Devices - Synopsys
5:15 - 6:30pm Networking Reception & Demos


Hands-on Workshop
embARC Machine Learning Interface (MLI) Workshop

The embARC Machine Learning Inference (MLI) software library is optimized for low-power IoT applications that utilize convolutional neural networks (CNN) and recurrent neural networks (RNN). During this workshop, participants will get hands-on experience using the MLI library on the Synopsys ARC EM processor, by building an application which uses a CNN to recognize hand-written characters.


Registration for the workshop opens in July. Stay tuned for additional details.


AI/Machine Learning Track

Creating Intelligent Facial Landmark Tracking Applications with DesignWare EV Processors
Dr. Yi-Ta Wu, VP of Engineering, ULSee

Real-time, dynamic face tracking is key for virtual try-on, augmented reality, and driver safety applications. In this presentation, we will describe applications that use facial landmark tracking. We will discuss some critical challenges that we addressed to account for lighting, clothing, and other variables for deployments to Volkswagen, Uniqlo, Disney, and more. We will explain how the MetaWare EV toolchain and DesignWare EV Processors help accelerate the development of SoCs for advanced driver assistance systems (ADAS), driver monitoring systems (DMS), and visual try-on applications.


Using Artificial Intelligence to Harness the Coming Data Explosion
Michael Thompson, Senior Product Marketing Manager, Synopsys

We are in the midst of a data explosion. Autonomous vehicles, augmented reality, machine vision, the internet and augmented reality are all increasing rapidly in capability. The common link in these capabilities is the large amounts of data that they generate. Most of the data is being created outside of the data center and transporting data from where it resides to the core or cloud for processing is becoming challenging. As data grows Artificial Intelligence will be used to manage it focusing on where data is stored, when it is moved and where it is processed. Offline processing will also increase, and AI can be used to process the data and then move it later to the cloud as needed. This presentation will look at the challenges that we face with data and how artificial intelligence can be used to overcome them.


Partitioning Graphs Across Multiple CNN Engines for Performance & Latency Improvement
Bo Wu, Senior Applications Engineer, Synopsys

There is often a demand to maximize inference performance on a given system. This presentation will introduce partitioning techniques designers can use with the EV6x CNN 3520 to improve design metrics, including performance, bandwidth and latency. We will discuss various application scenarios for single and multiple CNN graphs, and show, by way of examples, how to use the CNN inference APIs supplied with the MetaWare EV Development Toolkit to parallelize operations and increase performance. The presentation will conclude with a demo comparing the performance of the MobileNet CNN graph running on CNN 880, 1760 and 3520, and an analysis of the execution using the Percepio Tracealyzer tool.


Applying New Vision and Deep Learning Trends to Edge Applications
Gordon Cooper, Product Marketing Manager, Synopsys

Embedding computer vision and deep learning at the edge remains challenging today because of the huge computational and memory requirements and due to the pace of innovation of algorithms for modern vision and sensing tasks. CNN graphs particularly are rapidly evolving to improve the accuracy and speed of learning and inference. Mapping these vision and deep learning algorithms on low power embedded platforms are demanding on computational complexity, bandwidth and accuracy. In this presentation, we will discuss the latest computer vision trends and deep learning techniques for embedded platforms and how these trends are shaping the latest enhancements to the DesignWare EV Embedded Vision Processor IP family.



Automotive Track

System Modelling for Real-Time Automotive Applications using Deep Learning and Complex Data Processing
Juergen Schaefer, Lead Principal Mixed Signal Architecture, Infineon

Innovation in the automotive industry is defined by autonomous driving and reduction of CO2 emissions. For the next 15 years, the industry will develop cars with combustion engines, battery electrical vehicles and hybrid cars. To minimize CO2 emissions globally for the mix of these different powertrain architectures, predictive system control strategies have to be used. For this purpose, the characteristic of the powertrain architecture has to be described with corresponding system models. Several mechanical and thermomechanical elements of the powertrain are not representable by linear differential equations. Artificial Neural Networks (ANNs) and stochastic algorithms like particle filters are methods to get mathematical models for such non-linear elements. Kalman Filters and ANNs are used for the predictive based system control approaches. The topology of these algorithms use matrix-vector operations and vector-vector operations together with non-linear mathematical base functions. To fulfill the performance requirements for a real-time automotive application like powertrain, these algorithms has to be executed on a powerful VDSP architecture like Synopsys’ ARC EV6x processors.


ISO 26262 Compliant IP and SEooCs – Getting it Right!
Alexander Griessing, exida

Automotive safety IPs and SEooCs are offered left and right! “ASIL-D with Certification” – Product announcements and press releases promise it all. However, users soon realize how much work is left to be done and that certified components are often not as magical as advertised.

This presentation gives a clear overview and guidance, how ISO 26262 compliant IP and SEooC must be specified and designed, and which additional safety collateral and information must be provided to enable proper integration. Users are advised what to ask for, what to accept or reject, and how to work around some typical shortcomings of their suppliers.


Using MathWorks MATLAB with ARC MetaWare Development Toolkit
Hugh O’Keeffe, Engineering Director, Ashling

MathWorks MATLAB/SIMULINK is a mathematical programming platform allowing the development of algorithms, data analysis, and the creation of models and applications. The MetaWare MATLAB/SIMULINK plugin integrates the Synopsys DesignWare MetaWare Development Toolkit into MATLAB/SIMULINK, allowing compilation of generated ‘C’ language models and applications into highly-optimized code tuned for running on Synopsys DesignWare ARC targets. This presentation will provide an overview of how the plug-in works and demonstrates its usage with MATLAB designs.


Advanced Vector Floating Point DSP Processing for Automotive Applications
Graham Wilson, Product Marketing Manager, Synopsys

Automotive applications such as Advanced Driving Assist Systems (ADAS) and Engine Management, PowerTrain require increasing level of complexity as well as high level of precision and accuracy in terms of algorithms and data formats. As algorithm complexity grows, system architects are developing their algorithms with tools such as MATLAB, which work in high precision data formats such as half and single precision floating point.

These large amounts of computation need a specific core for large vector floating point DSP processor. The EV6x processor has 3 dedicated vector floating point computation pipes that gives industry leading level of throughput, as well as hardware acceleration for linear algebra mathematical functions.



IoT/Comms Track
Addressing IoT Connectivity Challenges with Low-power NB-IoT Modem Solutions
Iboun Sylla, IoT Product Marketing and Chip Architect, Palma Ceia SemiDesign

Low power IoT connectivity requires modem chipsets and integrated wireless options to enable cost-effective deployment. Narrow-band IoT (NB-IoT) is a key 3GPP cellular communication standard that makes this possible. This talk will cover the aspects of the NB-IoT protocol that make it a “go-to” technology for IoT and will highlight how both Palma Ceia SemiDesign and Synopsys applied their respective IP to provide a complete NB-IoT solution, shortening the time-to-market for developing IoT communication products such as multimode edge-based IoT devices or stand-alone chipsets.


Verifying the Security of ARC® Processor-based Systems with Radix-S
Dr. Nicole Fern, Hardware Security Engineer, Tortuga Logic

Security is a first-order design requirement for processor-based systems. Processor designers implement security functionality directly into the hardware itself to protect the system at its most fundamental layer. System integrators that use processor IP such as Synopsys’ DesignWare® ARC® processors must ensure that they configure and manage the protection and security features correctly, and that they do not introduce vulnerabilities.

Evaluating the security levels and vulnerabilities of complex, highly combined hardware-software systems is hard. In this talk, we outline a general methodology for combined hardware-software security verification for ARC-based platforms using Tortuga Logic’s Radix-S software. We demonstrate how Radix-S can be used to detect security vulnerabilities resulting from misconfiguration of hardware security features by creating an example system comprised of the ARC processor and vulnerable software that configures the memory protection unit incorrectly. With Radix-S, we quickly identify the flaw using standard functional verification techniques. Furthermore, we show how system integrators can verify the security of secure debug logic with this technology.


Embedded Multicore Application Development with Zephyr and ARC Processors
Alexey Brodkin, Software Engineering Manager, Synopsys

Performance in Desktop, Server and HPC applications has been scaling rapidly in recent years via multicore, continuously increasing the number of cores on a processor chip. The same principle has been extending to embedded systems, where multicore designs are increasingly more pervasive in embedded applications such as 5G data processor, edge IoT machine learning and many more.

This presentation will examine multicore application options and considerations using the Zephyr RTOS. We will introduce the Zephyr RTOS, its main features and multicore support models (AMP and SMP). We will discuss challenges associated with designing high-performance software applications for multicore and contrast AMP and SMP approaches using samples applications on modern ARC processors.


Enabling Ultra-High Performance, Low-Power 5G Modem Designs with Heterogeneous Multicore Systems
Graham Wilson, Product Marketing Manager, Synopsys

The ITU 5G standard pushes the requirements on wireless communication equipment for greater than 1Gbps data rates with reduced system latency, allowing an expansion of 5G use cases to automotive and other timing-critical IoT applications. SoC modem developers for 4G systems previously met performance requirements with heterogeneous systems, using multiple task-specific processor cores.

User Equipment (mobile devices) 5G modem SoCs will need to take the heterogeneous implementation further to provide greater computation for higher data rates, larger MIMO configurations, and lower latency, while maintaining similar power budgets to 4G modems. This session will go through the range of digital signal processors, controller cores, task-specific cores, and system connection schemes that will allow 5G mobile modem SoC developers to implement the required amount of programmability/flexibility in their design, while achieving the performance and low-power requirements.


Speed, Accuracy, Performance, and Visibility - ARC Processor Simulation without Compromise!
Igor Böhm, Software Architect and Technical Lead, Synopsys

Instruction set simulators (ISS) are vital for compiler, operating system, and application development, as well as processor architecture design space exploration and verification. Because the demands for each are so different, designing an ISS that caters to all of the above application scenarios is a constant challenge. In this session we first want to show the versatility of the DesignWare ARC nSIM simulator by demonstrating how it addresses all of the above requirements. Finally, we will highlight the latest feature of nSIM, its high-speed cycle-approximate simulation mode (NCAM). We will show key NCAM use-cases such as how to arrive at the best hardware configuration, derive the best compiler optimizations, and have a fully optimized application much before final silicon is available.


Next-Generation Voice and Audio Streaming Technology for Wearable Devices!
Graham Wilson, Product Marketing Manager, Synopsys

Wearable devices are fast becoming the next battle ground in terms of consumer product focus and differentiation. Smart Watches and fitness devices have become mainstream, with devices in the ear showing strong future growth. Hearing aids are becoming available over the counter, hence need to compete against commercial ear pod devices. These products look to offer voice, audio streaming with medical, biometric sensing capability connected to a smart phone device via Bluetooth communications standard.

Recently the Bluetooth SIG has been working on a Low Complexity Communications Codec (LC3) targeted towards ultra-low power wearable devices. This codec has been ported and optimized to the Synopsys ARC EM and HS processors which offer high performance and ultra-low power, ideally suited for battery operated wearable devices.