ARC Processor Summit 2017

Your Embedded Edge Starts Here
Tuesday, September 26th, 2017
8:30 a.m. - 7:00 p.m. PDT
Santa Clara Marriott
2700 Mission College Boulevard, Santa Clara, CA 95054


As embedded systems become more complex and integrate greater functionality, SoC developers are faced with the challenge of developing more powerful but also more energy-efficient devices. The processors used in these embedded applications must be efficient to deliver high levels of performance within limited power and silicon area budgets.

Join us at Synopsys' ARC® Processor Summit to learn about the latest technologies and trends in embedded processor IP, software, programming tools and applications. This free one-day event consists of multiple tracks and over 25 sessions in which experts from Synopsys, partners and the ARC user community will discuss challenges and solutions for a variety of topics including IoT security, automotive safety, embedded vision and much, much more.

During lunch we will have a Birds of a Feather session giving you the opportunity to meet with industry experts and others interested in similar topics. If there is a topic you’d like represented, please submit your idea to birdsofafeather@synopsys.com subject line “Birds of a Feather."


Time Description
8:30-9:00am Check-in and Breakfast
9:00-9:15am Opening Remarks: Yankin Tanurhan, Synopsys
9:15-10:15am Keynote: How AI, Deep Learning and Machine Perception are Changing Our World
Jeff Bier, Embedded Vision Alliance/BDTi
10:15-10:30am Break
Hardware Track Software Track Embedded Vision Track
10:30-11:00am Living on the IoT Edge: Doing More with Less - Synopsys Detecting and Avoiding Common RTOS-related Bugs - Percepio (10:30am-11:15am) Eliminate Processor Bottlenecks with Tightly Integrated Processing Units for Embedded Vision - Synopsys
11:00am-11:30am Accelerating DSP Algorithms using ARC Processor EXtension (APEX) Technology in ARC EM9D/11D Processors - Synopsys The Zephyr Project: This Year, Next Year - Zephyr Project (11:15am-11:45am)
11:30am-12:00pm IoT Demo Platform: Foundry, IP, Services - Brite Semi Programming DSP Processors Efficiently and with Ease - Synopsys (11:45am-12:30pm) New and Emerging Standards for Embedded Vision Programming - Khronos
12:00pm-12:30pm Using Design Time Analysis to Test Security Countermeasures Implemented in ARC SEM Processors - Riscure Automated Parallel Kernel Processing using OpenVX - Synopsys
12:30pm-1:30pm Lunch with "Birds of a Feather" Discussions and Demos
1:30pm–2:00pm No More Excuses: Secure Your SoC from IP Building Blocks to End-to-End Systems - Synopsys Sound Processing in Smart Home Devices - A System Approach - Alango Technologies OpenCL C for Efficient Programming of SIMD Machines - Synopsys
2:00-2:30pm OpenThread: Tales from the Front Lines - Synopsys Efficient Acceleration of OpenCV on Next-generation EV6x Vision Processor - PathPartner
2:30pm–3:00pm Ultra-low Power 3D Micro-GPU for IoT Devices with a DesignWare ARC EM5D Processor - Think Silicon Building an Embedded Linux Distribution for Your ARC Platform - Synopsys Scene Classification: Deep Learning for Mobile - Morpho, Inc.
3:00pm–3:45pm Play it Safe with the ARC EM Safety Island - Synopsys Full-featured Hardware Platforms to Accelerate Your ARC Software Development - Synopsys The Evolving Neural Network: Understanding and Applying the Latest CNN Techniques - Synopsys
3:45pm-4:00pm Break
4:00pm-4:30pm Machine Learning for Low-power IoT Devices - Synopsys (4:00pm-4:45pm) Secure, Java-programmable Ecosystem on ARC SEM Cores for End-point Devices with Sensors and Data Processing Capabilities - jNet ThingX Progressive Pruning of CNNs to Reduce Memory Size and Bandwidth - MulticoreWare
4:30pm-5:00pm The Secrets of Building Secure IoT Edge Devices: ARC SecureShield - Synopsys Practical Considerations for Mapping a CNN Graph to an Embedded Vision Processor - Synopsys
5:00pm-5:30pm Enabling Performance-intensive RISC and DSP Applications with New Superscalar ARC HS4x/D Processors - Synopsys (4:45pm-5:30pm) Easing Trace Debug in SoCs with Multiple Processor Architectures - Synopsys
5:30pm-7:00pm Networking Reception and Demos




9:15am - 10:15am
Keynote: How AI, Deep Learning and Machine Perception are Changing Our World
Jeff Bier, Founder, Embedded Vision Alliance and President, BDTI
Just a few years ago, it was inconceivable that everyday devices would incorporate human-like sensory perception. Now it’s clear that sophisticated perception will soon be ubiquitous in many types of systems. How soon? Faster than you might think, thanks to three key accelerating factors.
In a very short time, we're seeing roughly a 10X improvement in cost-performance and energy efficiency at each of three layers: algorithms, software techniques, and processor architecture. Combined, this means that we can expect roughly a 1,000X improvement. So, tasks that today require hundreds of watts of power and hundreds of dollars' worth of silicon will soon require less than a watt of power and less than a dollar's worth of silicon. This will be world-changing, enabling even very cost-sensitive devices, like toys, to incorporate sophisticated visual perception.
In this talk, I’ll show how innovators across the industry are delivering this 1,000X improvement very rapidly. I’ll also explain the relationships between artificial intelligence, machine learning, deep learning, and machine perception. Finally, I’ll illustrate through examples how these technologies are transforming many types of products, and highlight important challenges that remain.


Hardware Track

10:30am - 11:00am
Living on the IoT Edge - Doing More with Less
Fergus Casey, R&D Director, Synopsys
The Internet-Of-Things (IoT) market is causing the focus of IC design flows to shift from increasing performance to reducing power in order to meet the demands of battery-operated devices. For many of these applications, the opportunities to replace (or even recharge) batteries are limited. Power-efficient processors are critical to reducing the overall power profile required by IoT ICs. This presentation will provide an overview of ARC EM processor features and techniques to increase energy efficiency, extending your IoT edge products’ life expectancy in the wild.

11:00am - 11:30am
Accelerating DSP Algorithms using ARC Processor EXtension (APEX) Technology in ARC EM9D/11D Processors
Abhishek Bit, CAE, Synopsys
Code efficiency and performance are critical requirements for modern digital signal processing systems. This session will present some key techniques and processor architecture features that can be used to accelerate typical digital signal processing algorithms. DSP examples and optimization strategies will be presented for the DesignWare ARC EM9D and EM11D Processors. ARC Processor EXtension (APEX) technology can accelerate such algorithms, significantly reducing memory footprint. The performance benefits obtained by using APEX can be further leveraged using the XY memory architecture on ARC EM9D and EM11D Processors.

11:30am - 12:00pm
IoT Demo Platform: Foundry, IP, Services
John Zhuang, CTO, Brite Semi
The IoT market is filled with IoT platforms, many saving customers’ development time. Experience has proven that while reducing time to market is important, it is not the only thing required to build a successful platform. Brite Semi will discuss a new IoT Platform developed in a collaboration with SMIC and Synopsys that enables OEMs, system integrators, and startups to leverage a platform with innovative technologies from foundry, to IP & subsystems, and full spec to chip services.

12:00pm - 12:30pm
Using Design Time Analysis to Test Security Countermeasures Implemented in ARC SEM Processors
Jasper van Woudenberg, CTO, Riscure North America
Products in markets including automotive, IoT and payment need high levels of security. One of the main challenges in creating secure systems is to keep encryption keys secure and difficult to derive by an adversary. Side-channels attacks, such as power consumption analysis on data dependent computations, are a known attack to gain access to these encryption keys. Currently testing of side-channel resistant designs requires testing to be performed on the actual silicon. This presentation describes a new tool and methodology using Synopsys’ simulators with Riscure’s side channel analysis tool to test side-channel countermeasures’ effectiveness on an ARC SEM processor prior to implementing them in silicon. The use of this tool will result in fewer tape-outs, lower cost, and shorter time to market.

1:30pm - 2:30pm
No More Excuses: Secure Your SoC from IP Building Blocks to End-to-End Systems
Ruud Derwig, Software and Systems Architect, Synopsys
Despite the cybersecurity media hype, security is still an afterthought in many designs. Instead of proactive, differentiating, future-proof security designs, security is generally considered a nuisance forced by regulations or an ad-hoc solution triggered by security breaches. Lack of knowledge, additional cost, and complexity are the typical excuses used. The resulting vulnerabilities range from simple software misconfiguration to more complex vulnerabilities such as side-channel leakage. To address these security challenges Synopsys offers a scalable range of security IP building blocks that offer the combined efficiency and security required for IoT applications. This presentation will describe how Synopsys reduces complexity and mitigates knowledge roadblocks by pre-integrating hardware and software IP into a Secure Subsystem that seamlessly fits into already standardized end-to-end security solutions like embedded SIM.

2:30pm - 3:00pm
Ultra-low Power 3D Micro-GPU for IoT Devices with a DesignWare ARC EM5D Processor
Iakovos Stamoulis, CTO and Co-Founder, Think Silicon
The emerging Internet-of-Things market, with display devices limited in area, performance, memory, thermal dissipation and battery capacity is adding design challenges for engineers. The end-user is expecting the same fluid interaction and high–quality graphical-user-interface (GUI) experience known from their smart phones and tablets. Synopsys and Think Silicon developed a prototype sporting an ARC EM5D Processor with a NEMA®-GPU including NEMA® |GFX-API. The solution is aimed for developers to rapidly implement high-quality 3D graphics in connected ultra-low-power wearables and embedded devices with reduced risk and cost.

3:00pm - 3:45pm
Play it Safe with the ARC EM Safety Island
Srini Krishnaswami, ASIC Digital Design Engineer, Synopsys
Developing ISO 26262 certified safety-critical automotive systems has created a new set of processing challenges for IC suppliers. This presentation will provide an overview of the key challenges to achieve ASIL D certification in a complex SoC and how ASIL D ready certified ARC EM Safety Island IP together with Synopsys STAR memory and logic test solutions can accelerate the development, verification, and certification process of automotive SoCs, reducing the overall safety investment within your SoC.

4:00pm - 4:45pm
Machine Learning for Low-power IoT Devices
Anatoly Savchenkov, Software Engineering Manager, Synopsys
Use of machine learning algorithms in IoT is proliferating dramatically. Multisensory context awareness, natural human to machine interfaces, and decision-making in various disciplines such as mechanical fault detection and personal healthcare are just a few examples of applications that would not be possible without these algorithms. The technology is migrating from traditional cloud-based services to local devices for better efficiency, autonomy and privacy. The multitude of artificial neural network classes and constantly increasing model complexity present a number of challenges for systems developers. This session presents approaches to solving the challenges of using machine learning technologies in low-power IoT devices.

4:45pm - 5:30pm
Enabling Performance-intensive RISC and DSP Applications with New Superscalar ARC HS4x/D Processors
Carlos Basto, ASIC Digital Design Engineer, Synopsys
Next-generation embedded applications such as human-machine interfaces for virtual reality require very high performance and a combination of RISC and DSP processing. Synopsys’ new HS4x/D processor family is designed to deliver this performance. These new high-performance processors deliver multi-issue, multi-core capabilities and combine RISC and DSP processing to maximize performance while minimizing power consumption, memory requirements and system resources. This session will look at the capabilities of the new family and how they can be used to address performance-intensive mixed-signal embedded applications.


Software Track

10:30am - 11:15am
Detecting and Avoiding Common RTOS-related Bugs
Niclas Lindblom, Field Application Engineer, Percepio AB
Real-time operating systems (RTOSes) are increasingly common in the development of embedded software, due to increasingly complex and connected applications that often benefit from multi-threading. However, introducing an RTOS may bring new types of software problems related to timing, synchronization and resource usage; elusive bugs that may slip out into production code. This talk will discuss common RTOS-related bugs, why they occur and “best practices” in embedded software design for avoiding them. We also present techniques and tools for visualization and analysis of RTOS-related issues, to provide better insight and thereby facilitate debugging and general understanding of the runtime events.

11:15am - 11:45am
The Zephyr Project: This Year, Next Year
Kate Stewart, Sr. Director of Strategic Programs, Linux Foundation
Zephyr is an upstream open source project for devices where Linux is too big to fit. This talk will overview the progress we've made in the first year towards the projects goals around incorporating best of breed technologies into the code base, and building up the community to support multiple architectures and development environments. We will share our roadmap, plans and the challenges ahead of the us and give an overview of the major technical challenges we want to tackle in the next year.

11:45am - 12:30pm
Programming DSP Processors Efficiently and with Ease
Pieter van der Wolf, Principal Product Architect, Synopsys
The ARC EM and HS processor families both offer processors with the ARCv2DSP ISA extension to support a wide range of DSP applications. These DSP processors come with an advanced tool suite, including a powerful DSP compiler, to support C-level programming of DSP applications. In this presentation we show how excellent results, in terms of high performance and small code size, can be achieved with high-level DSP programming. Ease of programming is also supported with an extensive library of DSP functions. The high-level programming enables software compatibility across different ARC DSP processors.

1:30pm - 2:00pm
Sound Processing in Smart Home Devices – A System Approach
Robert Schrager, Director of Sales and Marketing, Alango Technologies
Speech, as the most natural way we express ourselves, has tremendous potential as a method of human-machine interface. Speech recognition technologies have improved significantly but are still dependent on factors that influence the signal to “noise” ratio. During the last three years Alango, a leading provider of speech and audio enhancement DSP technologies, has accumulated significant practical experience in integration of front-end speech enhancement and speech recognition. In this presentation we will discuss all aspects of signal processing in Smart Home devices, including multi-microphone beamforming, echo cancellation, as well as keyword recognition and the computational resources necessary to perform such tasks. We’ll discuss both technology and system aspects. Additionally, we will share our vision for the voice interface of the future and discuss R&D topics to make it a reality.

2:00pm - 2:30pm
OpenThread: Tales from the Front Lines
Francois Bedard, Senior R&D Manager, Operating Systems and Open Source Software, Synopsys
The Thread protocol from the Thread Group has seen strong adoption as an industry standard for Smart Home connectivity. In this talk we will look into the capabilities of the Thread protocol and share experiences from porting the OpenThread open source implementation of the Thread specification protocol stack to the ARCv2 architecture, targeting the ARC EM Starter Kit platform.

2:30pm - 3:00pm
Building an Embedded Linux Distribution for Your ARC Platform
Alexey Brodkin, Senior Software Engineer, Synopsys
Linux is a robust operating system that provides a rich set of capabilities to embedded systems. However, building and maintaining a Linux distribution for embedded platforms can seem like a daunting task to the first-time user. In this session, an expert from our open source team will review several options and provide tips and insights for successfully creating and maintaining your own embedded Linux distribution.

3:00pm - 3:45pm
Full-featured Hardware Platforms to Accelerate Your ARC Software Development
Wido Kruijtzer, Senior Manager, ASIC Digital Design, Synopsys
Starting software development early is a requirement for meeting the ever-shortening development cycles for complex SoC projects. Having the right hardware platform for that purpose, along with the associated software support, is key to achieving success. Synopsys provides a variety of platforms for software development on ARC processors. The platforms range from FPGA-based starter kits to full-speed silicon-based platforms with a rich set of peripherals and comprehensive extensibility options. The platforms are supported by the tools and software necessary to develop bare-metal, RTOS and, in the case of ARC HS processors, Linux and other high-end applications. In this session, we will provide an overview of several of the available platforms and examine the software support available to speed application development on ARC.

4:00pm - 4:30pm
Secure, Java-programmable Ecosystem on ARC SEM Cores for End- Point Devices with Sensors and Data Processing Capabilities
Mikhail Friedland, CEO & President, jNet ThingX Corp
When creating distributed IoT control systems, we rely on edge devices or end-points. But, are these devices secured against cyber-attacks? Design teams working on these projects require multi-discipline engineering talent that includes embedded hardware and software engineers, protocol designers, and crypto experts. This session presents a software development environment and platform that accelerates time-to-market by removing these complexities and has helped secure billions of SIMs, smart cards and ePassports. It provides a secure Java-programmable system running on ARC SEM cores to power IoT devices with sensor-awareness and multi-protocol SoC connectivity.

4:30pm - 5:00pm
The Secrets of Building Secure IoT Edge Devices: ARC SecureShield
Ruud Derwig, Software and Systems Architect, Synopsys
Developing bug-free software is complex and costly. Buffer overruns and other software errors still rank high in Common Weakness Enumeration (CWE) statistics. SecureShield™ cannot stop users from writing vulnerable software, but it helps contain the resulting vulnerabilities. Software in a device comes from sources with different trust levels: internal development, external suppliers, open source, and maybe even end-users. Different software modules also have different protection requirements. SecureShield technology helps isolate these different classes of software and uses least-privilege access control to protect system resources, optimized for low power/cost IoT edge devices. This presentation introduces SecureShield, provides an update on latest features, and demonstrates these features with the Agile Crypto Platform solution jointly developed by InfoSec Global and Synopsys.

5:00pm - 5:30pm
Easing Trace Debug in SoCs with Multiple Processor Architectures
Fergus Casey, R&D Director, Synopsys
ARC Real-Time Trace (RTT) is an efficient way to capture the behavior of a program: not only instruction trace, but register and memory changes as well. Trace data can be captured at high rate and uploaded to the debugger at Gigabit Ethernet speeds.
The ARC trace portfolio eases the hardware integration burden in SoCs with heterogeneous processor architectures by reducing trace logic and pin overhead in designs that include a mix of ARM and ARC processors, while also streamlining the debug experience for the firmware teams. This presentation explains the ARC trace architecture together with CoreSight support using the Lauterbach Trace32 debug platform.


Embedded Vision Track

10:30am - 11:30am
Eliminate Processor Bottlenecks with Tightly Integrated Processing Units for Embedded Vision
Gordon Cooper, Product Marketing Manager, EV Processors, Synopsys
As embedded vision processing performance requirements increase and power and area goals remain aggressive, embedded engineers looking for the most optimized performance and power solution for vision are turning toward high-performance embedded vision processors tightly coupled with dedicated neural network engines. This presentation will describe how embedded vision processors, offering a combination of tight integration and scalability, can efficiently support high performance vision applications such as surveillance, autonomous driving and augmented reality.

11:30am - 12:00pm
New and Emerging Standards for Embedded Vision Programming
Radhakrishna Giduthuri, Member of OpenVX and NNEF Working Groups, AMD
The landscape of APIs for accelerating vision and neural network software using specialized processors continues to rapidly evolve. Many industry-standard APIs, such as OpenCL and OpenVX, are being upgraded to increasingly focus on deep learning, and the industry is rapidly adopting the new generation of low-level, explicit GPU APIs, such as Vulkan, that tightly integrate graphics and compute. Some of these APIs, like OpenVX and OpenCV, are vision-specific, while others, like OpenCL and Vulkan, are general-purpose. Some, like CUDA and TensorRT, are vendor-specific, while others are open standards that any supplier can adopt. Which ones should you use for your project?

12:00pm - 12:30pm
Automated Parallel Kernel Processing using OpenVX
Vineet Gupta, R&D Engineer, Synopsys
OpenVX is the software framework that combines the different heterogeneous components of the embedded vision system -- including scalar processing, vector DSP processing and deep learning with a CNN accelerator. This presentation will introduce OpenVX using an example embedded vision solution.

1:30pm - 2:00pm
OpenCL C for Efficient Programming of SIMD Machines
Seema Mirchandaney, Software Engineering Manager, Synopsys
This presentation will focus on the benefits and ease of programming vision-based kernels using the key features of OpenCL C. The language extensions that allow programmers to take advantage of hardware features typical of embedded vision processors, such as wider vector widths, sophisticated accumulator forms of instructions, and scatter/gather capabilities, will be described. Advanced topics, such as whole function vectorization support available in the compiler and the benefits of hardware support for predication in the context of lane-based control flow and OpenCL C will also be covered.

2:00pm - 2:30pm
Efficient Acceleration of OpenCV on Next-generation EV6x Vision Processor
N Vinith Kumar, Senior Technical Lead, PathPartner
OpenCV is an open source library of 2500 vision algorithms that help build vision applications. This presentation will discuss which OpenCV algorithms are most important for embedded vision and will cover optimization techniques for getting the best performance out of these library functions.

2:30pm - 3:00pm
Scene Classification: Deep Learning for Mobile
Toshi Torihara, Vice President, Morpho US, Inc.
There is a growing need for neutral network configurations that are suitable for edge processing using Deep Learning technology in the embedded system industry, and demand for a reduction in computing load has also been increasing. This presentation will discuss the optimization of Morpho's image recognition engine on Synopsys's DesignWare® EV6x Vision Processors to realize high performance and real-time image processing in system-on-chip products. Morpho capabilities include image enhancement technology which combines deep learning and computational photography.

3:00pm - 3:45pm
The Evolving Neural Network: Understanding and Applying the Latest CNN Techniques
Gordon Cooper, Product Marketing Manager, EV Processors, Synopsys
The advances in computer vision research are continuing at a fast pace with rapid transitions from research topic to a implemented technology. This presentation will discuss the current and near future expectations for the evolving deep learning and embedded vision markets. Broader use cases for CNN will also be discussed -- like in radar and audio applications -- as well as other neural network techniques and applications involving RNNs.

4:00pm - 4:30pm
Progressive Pruning of CNNs to Reduce Memory Size and Bandwidth
Anshu Arya, Solution Architect, MulticoreWare
Research into CNN algorithms has evolved from finding the highest accuracy, to finding the highest accuracy with the least amount of computations. This presentation will discuss the latest techniques for graph pruning including a practical example and benchmark improvements.

4:30pm - 5:30pm
Practical Considerations for Mapping a CNN Graph to an Embedded Vision Processor
Bo Wu, CAE, EV Processors, Synopsys
In this presentation, you will learn the development flow and implementation considerations for moving from an academic CNN/deep learning graph to a commercial embedded vision design. The presentation will use practical examples that highlight the latest CNN graph mapping tool capabilities, including dispatched processing and pruning/compression. You will also learn about the cost vs. accuracy trade-offs of CNN bit width, balancing internal memory size and external memory bandwidth, and the importance of keeping data local to the CNN processor to improve bandwidth. Key deep CNN/learning benchmarks will be discussed including VGG16, Yolo, Denoiser, and more.


Demos


DSP Pre-Processing in Voice Controlled Music Player – Alango Technologies
A demonstration of Alango’s Voice Enhancement Package (VEP). VEP is a suite of real-time software DSP technologies designed for improving speech recognition performance in multi-microphone voice controlled multi-media devices. The stereo music player demonstrated includes a 4 microphone array, Alango VEP pre-processing, and ASR software. VEP functionality demonstrated include stereo acoustic echo cancellation and beamforming.

Real-Time Trace for ARC Processors – Ultra-XD Hardware Trace Probe – Ashling
The Ultra-XD Trace Probe allows you to capture trace from an ARC HS or EM core and upload it to the MetaWare Debugger at gigabit Ethernet speeds. Captured trace can be turned into a “replay” database enabling you to debug your program by executing it both forwards and backwards. Developed in cooperation with Synopsys, the Ultra-XD probe integrates with the MetaWare or GNU GDB Debuggers under Windows or Linux based hosts.

55-nm IoT Reference Platform – Brite Semi
This demonstration features a collaboration between Synopsys, Brite and SMIC that leverages Synopsys’ DesignWare ARC Data Fusion IP Subsystem and Brite’s test chip in SMIC’s 55-nm ultra-low-power process. Applications such as voice activation, gesture recognition, face detection and 9D sensor fusion are showcased. This ASIC platform significantly increases performance, lowers power consumption and reduces system cost for always-on IoT applications.

eSIM Software Stack for ARC Platforms - Cellnetrix
This demo covers the major capabilities of the Cellnetrix eSIM Software Stack on the ARC Secure IP Subsystem. It demonstrates the main use-cases of GSMA Remote SIM provisioning for IoT and consumer devices, such as in-the-field remote device activation with initial subscription and provisioning of a new subscription. This technology enables mobile devices to be remotely provisioned over the air without physical SIM cards in a secure and reliable way. Multiple operator profiles can be provisioned to, and used by, a device. The demo setup includes subscription management platform SM-DP+, mobile device simulation and features the ARC EM Starter Kit board running the eSIM software.

AgileSec Trust Management Root - InfoSec Global
The AgileSec Trust Management Root (TMR) is an application for ARC processors that can provision security domains to ensure secure loading, installing and managing of Agile Crypto libraries in the SecureShield TEE. This demo will go through the life cycle of creating security domains, establishing secure channels, provisioning keys and certificates, loading Agile Crypto libraries within SecureShield at runtime, and making the crypto library available to applications running on ARC processors.

Securing the Internet of Things with Unique Device Identities on ARC EM Processors - Intrinsic ID
Intrinsic ID creates unique device identities which serve as the basis for essentially all security primitives. Combined with the SecureShield Technology from Synopsys, Intrinsic ID security can be optimized for performance when used in conjunction with ARC Cryptopack APEX accelerators. Intrinsic ID security technology is ideally suited to provide root keys and unique identities in low-power Internet of Things devices such as wearables, thermostats and automotive connectivity systems and applications. Synopsys and Intrinsic ID technology combine to deliver secure and reliable crypto key management to ARC EM ultra-low power processors.

Designing a Smart Lock with a Java Secure Node - jNet ThingX
This demo shows an ARC SEM processor node interfacing with a Bluetooth connected Smart Lock to establish secure symmetric-based message exchange leveraging Elliptic Curve Cryptography with Diffie-Hellman key exchange algorithms. With this system, a roughly 5x productivity boost is made possible by deploying a Java-based solution rather than developing on bare metal and conventional programming techniques. It also drastically lowers the complexity bar, allowing developers without in-depth cryptographic skills to deploy secure solutions.

Lauterbach TRACE32 Debugging of DesignWare ARC Processors - Lauterbach
The demonstration will show debugging of an ARC EM Starter Kit target using the Lauterbach TRACE32 debugger. It will demonstrate source-level code debugging, debugging using full on-chip breakpoints with multiple types of breakpoints including program breakpoints, address read/write breakpoints, data breakpoints for memory writes and breakpoints on auxiliary registers. Lauterbach supports debugging of all ARC cores, including multicore debugging and support for Real Time Trace (RTT) on ARCv2 cores.

Morpho Computational Photography & Deep Learning Solutions – Morpho Technology
Morpho develops software for use in vision processors for mobile, automotive, broadcasting, and medical markets etc. In this demo, Morpho will show a variety of computational photography and deep learning software algorithms that are used for applications such as scene classification and video stabilization.

Low-Light Object Recognition Using OpenCV – PathPartner
For autonomous vehicles to function correctly in their environment, they must be able to perform consistently in multiple lighting circumstances. This demonstration shows the results of PathPartner's low-light enhancement algorithm executing traffic-sign recognition on a convolutional neural network (CNN).

Visualizing RTOS Behavior – Percepio
Using FreeRTOS running on an ARC EM Starter Kit, Percepio will showcase the possibilities that software tracing opens up. Percepio Tracealyzer presents a comprehensive view of how your RTOS-based application behaves during runtime and makes it easy to spot irregularities and potential bugs. Tracealyzer offers several views of the trace log and the views are connected to each other, so that you can correlate a timeline of events with e.g. message flow or CPU load.

Think Silicon NEMA® 3D GPU for IoT class devices with ARC EM5D Processor – Think Silicon
Synopsys and Think Silicon developed a prototype sporting a DesignWare® ARC EM5D Processor with a NEMA®- 3D GPU including NEMA®|GFX-API, 9D-Sensor, 5” TFT LCD and is fully battery powered. The solution is aimed for developers to rapidly implement high-quality 3D graphics in connected ultra-low-power wearables and embedded devices with reduced risk and cost.

ARC Software Development at Full Speed - Synopsys
The ARC HS Development Kit (HSDK) contains an ASIC implementation of a quad-core ARC HS Processor and a rich set of peripherals including Ethernet, WiFi, Bluetooth, USB, I2C, SPI and UART. It is supported by the tools and software necessary to develop Linux, RTOS and bare-metal applications. Linux distributions can be built for the platform using the open-source Yocto Project and RTOS & bare metal applications can be developed with the embARC Open Software Platform (OSP). This demonstration will show the ARC HSDK in action as a great way to get started quickly with software development on ARC processors.

Complete Bluetooth Low Energy Link Layer and PHY IP - Synopsys
This demonstration features Synopsys’ complete DesignWare® Bluetooth Low Energy IP solution operating in two distinct roles – as a central device and a peripheral device. Synopsys’ Bluetooth Low Energy IP solution is compliant with Bluetooth 5 and Bluetooth mesh, and offers a compact, low-power wireless IP solution for IoT applications like wearables, smart home and smart city/industrial.

Protecting Cloud-Enabled IoT Devices - Synopsys
Ensuring secure authentication between IoT devices and their communication to the cloud is critical to protect everyday systems and applications. This demo shows the DesignWare tRoot Hardware Secure Module with Root of Trust connecting via the Transport Layer Security (TLS) protocol to the Amazon Web Services server, allowing secure remote control and status operations.

Real Time Object Detection with DesignWare EV6x Embedded Vision Processors - Synopsys
Security cameras and ADAS applications need to recognize objects in their surroundings. This live demo implements the TinyYOLO neural network on the EV6x Processor IP’s CNN engine to recognize and label items in the camera’s field of vision.

Zephyr Project – An Open Source RTOS for Secure IoT - Synopsys
The Zephyr Project is a small, scalable real-time operating system for use on resource-constrained systems, including ARC EM Processors. As a true open source project, the community can evolve the Zephyr Project to support new hardware, developer tools, sensor and device drivers. The demonstration will show a sensor fusion application running on the Zephyr RTOS ported to the ARC EM Starter Kit. A Zephyr Project representative will also be available to answer questions on Zephyr and how to become part of the project.